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name:-0.018748044967651
name:-0.0038731098175049
Caillat; Christian Patent Filings

Caillat; Christian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Caillat; Christian.The latest application filed is for "method and apparatus for per-deck erase verify and dynamic inhibit in 3d nand".

Company Profile
4.16.15
  • Caillat; Christian - Boise ID
  • Caillat; Christian - Versonnex FR
  • Caillat; Christian - Wavre BE
  • Caillat; Christian - Grenoble FR
  • Caillat; Christian - Saint Egreve FR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Apparatus configured to program memory cells using an intermediate level for multiple data states
Grant 10,504,600 - Miccoli , et al. Dec
2019-12-10
Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND
Grant 10,346,088 - Righetti , et al. July 9, 2
2019-07-09
Method And Apparatus For Per-deck Erase Verify And Dynamic Inhibit In 3d Nand
App 20190102104 - Righetti; Niccolo ;   et al.
2019-04-04
Apparatus Configured To Program Memory Cells Using An Intermediate Level For Multiple Data States
App 20190088343 - Miccoli; Carmine ;   et al.
2019-03-21
Erasing memory segments in a memory block of memory cells using select gate control line voltages
Grant 10,153,049 - Caillat , et al. Dec
2018-12-11
Apparatus configured to program memory cells using an intermediate level for multiple data states
Grant 10,147,494 - Miccoli , et al. De
2018-12-04
Apparatus Configured To Program Memory Cells Using An Intermediate Level For Multiple Data States
App 20180211714 - Miccoli; Carmine ;   et al.
2018-07-26
Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
Grant 9,953,718 - Miccoli , et al. April 24, 2
2018-04-24
Erasing Memory Segments In A Memory Block Of Memory Cells Using Select Gate Control Line Voltages
App 20180068737 - Caillat; Christian ;   et al.
2018-03-08
Erasing memory segments in a memory block of memory cells using select gate control line voltages
Grant 9,779,829 - Caillat , et al. October 3, 2
2017-10-03
Programming Memory Cells To Be Programmed To Different Levels To An Intermediate Level From A Lowest Level
App 20170178737 - Miccoli; Carmine ;   et al.
2017-06-22
Erasing Memory Segments In A Memory Block Of Memory Cells Using Select Gate Control Line Voltages
App 20170140833 - Caillat; Christian ;   et al.
2017-05-18
Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
Grant 9,633,719 - Miccoli , et al. April 25, 2
2017-04-25
Programming Memory Cells To Be Programmed To Different Levels To An Intermediate Level From A Lowest Level
App 20160351253 - Miccoli; Carmine ;   et al.
2016-12-01
Method for manufacturing a dual work function semiconductor device
Grant 9,245,759 - Schram , et al. January 26, 2
2016-01-26
Techniques for providing a semiconductor memory device
Grant 9,093,311 - Van Buskirk , et al. July 28, 2
2015-07-28
Method for tuning the effective work function of a gate structure in a semiconductor device
Grant 9,076,726 - Kauerauf , et al. July 7, 2
2015-07-07
Techniques For Providing A Semiconductor Memory Device
App 20140291763 - VAN BUSKIRK; Michael A. ;   et al.
2014-10-02
Method for Tuning the Effective Work Function of a Gate Structure in a Semiconductor Device
App 20140187039 - Kauerauf; Thomas ;   et al.
2014-07-03
Semiconductor memory device
Grant 8,748,959 - Van Buskirk , et al. June 10, 2
2014-06-10
Method For Manufacturing A Dual Work Function Semiconductor Device
App 20140106556 - Schram; Tom ;   et al.
2014-04-17
Oxygen diffusion barrier comprising Ru
Grant 8,518,793 - Kim , et al. August 27, 2
2013-08-27
Oxygen Diffusion Barrier Comprising Ru
App 20130102121 - Kim; Min-Soo ;   et al.
2013-04-25
Integrated circuit comprising a transistor and a capacitor, and fabrication method
Grant 7,994,560 - Caillat , et al. August 9, 2
2011-08-09
Techniques For Providing A Semiconductor Memory Device
App 20100259964 - Van Buskirk; Michael A. ;   et al.
2010-10-14
Integrated Circuit Comprising A Transistor And A Capacitor, And Fabrication Method
App 20090121269 - Caillat; Christian ;   et al.
2009-05-14
Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated-circuit component
Grant 7,008,842 - Mazoyer , et al. March 7, 2
2006-03-07
Integrated circuit with dram memory cell
App 20040262638 - Mazoyer, Pascale ;   et al.
2004-12-30
MIS transistor and method for making same on a semiconductor substrate
Grant 6,562,687 - Deleonibus , et al. May 13, 2
2003-05-13
Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated-circuit component
App 20020162677 - Mazoyer, Pascale ;   et al.
2002-11-07

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