Cadouri; Eitan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cadouri; Eitan.The latest application filed is for "method and mechanism for extraction and recognition of polygons in an ic design".

Company Profile

0.17.6

Cadouri; Eitan - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and mechanism for extraction and recognition of polygons in an IC design Grant 8,429,588 - Irmatov , et al. April 23, 2	2013-04-23
Method And Mechanism For Extraction And Recognition Of Polygons In An Ic Design App 20110167400 - Irmatov; Anwar ; et al.	2011-07-07
Method and mechanism for performing partitioning of DRC operations Grant 7,913,206 - Cadouri March 22, 2	2011-03-22
Method and mechanism for extraction and recognition of polygons in an IC design Grant 7,908,579 - Irmatov , et al. March 15, 2	2011-03-15
Method and system for implementing parallel processing of electronic design automation tools Grant 7,904,852 - Cadouri , et al. March 8, 2	2011-03-08
Method and system for parallel processing of IC design layouts Grant 7,657,856 - Koshy , et al. February 2, 2	2010-02-02
Method and mechanism for performing latch-up check on an IC design Grant 7,617,465 - Cadouri November 10, 2	2009-11-10
Method and system for using pattern matching to process an integrated circuit design Grant 7,555,736 - Cadouri June 30, 2	2009-06-30
Adjusting die placement on a semiconductor wafer to increase yield Grant 7,508,071 - Cadouri March 24, 2	2009-03-24
Mapping yield information of semiconductor dice Grant 7,440,869 - Cadouri October 21, 2	2008-10-21
Method and mechanism for performing DRC processing with reduced passes through an IC design Grant 7,418,682 - Cadouri August 26, 2	2008-08-26
Optimization of die placement on wafers Grant 7,334,205 - Cadouri February 19, 2	2008-02-19
Method And Mechanism For Extraction And Recognition Of Polygons In An Ic Design App 20070288876 - Irmatov; Anwar ; et al.	2007-12-13
Selecting dice to test using a yield map Grant 7,220,605 - Cadouri May 22, 2	2007-05-22
Adjusting die placement on a semiconductor wafer to increase yield App 20070105273 - Cadouri; Eitan	2007-05-10
Selecting die placement on a semiconductor wafer to reduce test time Grant 7,190,183 - Cadouri March 13, 2	2007-03-13
Adjusting die placement on a semiconductor wafer to increase yield Grant 7,169,638 - Cadouri January 30, 2	2007-01-30
Semiconductor wafer with non-rectangular shaped dice App 20060278956 - Cadouri; Eitan	2006-12-14
Method and system for using pattern matching to process an integrated circuit design App 20060281200 - Cadouri; Eitan	2006-12-14
Transforming yield information of a semiconductor fabrication process Grant 7,039,543 - Cadouri May 2, 2	2006-05-02
Optimization of die placement on wafers Grant 6,826,738 - Cadouri November 30, 2	2004-11-30
Optimization of die placement on wafers App 20030212966 - Cadouri, Eitan	2003-11-13

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