| Patent | Date |
|---|
System for reconfiguring a processor array
Grant 8,103,866 - Butts January 24, 2 | 2012-01-24 |
System of virtual data channels in an integrated circuit
Grant 7,801,033 - Jones , et al. September 21, 2 | 2010-09-21 |
System and method for performing design verification
Grant 7,792,933 - Butts , et al. September 7, 2 | 2010-09-07 |
Emulation system with time-multiplexed interconnect
Grant 7,739,097 - Sample , et al. June 15, 2 | 2010-06-15 |
System For Configuring A Processor Array
App 20080235490 - Jones; Anthony Mark ; et al. | 2008-09-25 |
System For Reconfiguring A Processor Array
App 20080229093 - Butts; Michael R. | 2008-09-18 |
Logic multiprocessor for FPGA implementation
Grant 7,260,794 - Butts August 21, 2 | 2007-08-21 |
Processor Having Multiple Instruction Sources And Execution Modes
App 20070169022 - Jones; Anthony Mark ; et al. | 2007-07-19 |
Reconfigurable Processing Array Having Hierarchical Communication Network
App 20070124565 - Jones; Anthony Mark ; et al. | 2007-05-31 |
System of virtual data channels in an integrated circuit
App 20070025382 - Jones; Anthony Mark ; et al. | 2007-02-01 |
High-performance programmable logic architecture
Grant 6,882,176 - Norman , et al. April 19, 2 | 2005-04-19 |
System and method for performing design verification
App 20050022143 - Butts, Michael R. ; et al. | 2005-01-27 |
Logic multiprocessor for FPGA implementation
App 20040123258 - Butts, Michael R. | 2004-06-24 |
Memory circuit for use in hardware emulation system
Grant 6,732,068 - Sample , et al. May 4, 2 | 2004-05-04 |
Optimized emulation and prototyping architecture
Grant 6,625,793 - Sample , et al. September 23, 2 | 2003-09-23 |
Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
App 20030154458 - Butts, Michael R. ; et al. | 2003-08-14 |
Emulation system with time-multiplexed interconnect
App 20030074178 - Sample, Stephen P. ; et al. | 2003-04-17 |
Programmable logic device having integrated probing structures
Grant 6,539,535 - Butts , et al. March 25, 2 | 2003-03-25 |
Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
App 20020162084 - Butts, Michael R. ; et al. | 2002-10-31 |
Memory circuit for use in hardware emulation system
App 20020161568 - Sample, Stephen P. ; et al. | 2002-10-31 |
Optimized emulation and prototyping architecture
App 20020095649 - Sample, Stephen P. ; et al. | 2002-07-18 |
Emulation system with time-multiplexed interconnect
Grant 6,377,912 - Sample , et al. April 23, 2 | 2002-04-23 |
PLD with on-chip memory having a shadow register
Grant 6,353,552 - Sample , et al. March 5, 2 | 2002-03-05 |
Optimized emulation and prototyping architecture
Grant 6,289,494 - Sample , et al. September 11, 2 | 2001-09-11 |
I/O buffer circuit with pin multiplexing
Grant 6,285,211 - Sample , et al. September 4, 2 | 2001-09-04 |
Programmable logic device with multi-port memory
Grant 6,219,284 - Sample , et al. April 17, 2 | 2001-04-17 |
Look-up table based logic element with complete permutability of the inputs to the secondary signals
Grant 6,184,707 - Norman , et al. February 6, 2 | 2001-02-06 |
I/O buffer circuit with pin multiplexing
Grant 6,020,760 - Sample , et al. February 1, 2 | 2000-02-01 |
Programmable logic device with multi-port memory
Grant 6,011,744 - Sample , et al. January 4, 2 | 2000-01-04 |
Method for performing simulation using a hardware emulation system
Grant 6,002,861 - Butts , et al. December 14, 1 | 1999-12-14 |
Emulation system with time-multiplexed interconnect
Grant 5,960,191 - Sample , et al. September 28, 1 | 1999-09-28 |
Diagnostic interface system for programmable logic system development
Grant 5,870,410 - Norman , et al. February 9, 1 | 1999-02-09 |
Look-up table based logic element with complete permutability of the inputs to the secondary signals
Grant 5,821,773 - Norman , et al. October 13, 1 | 1998-10-13 |
Method for performing simulation using a hardware logic emulation system
Grant 5,812,414 - Butts , et al. September 22, 1 | 1998-09-22 |
Apparatus and method for performing computations with electrically reconfigurable logic devices
Grant 5,796,623 - Butts , et al. August 18, 1 | 1998-08-18 |
Method for implementing tri-state nets in a logic emulation system
Grant 5,734,581 - Butts , et al. March 31, 1 | 1998-03-31 |
Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation
Grant 5,661,662 - Butts , et al. August 26, 1 | 1997-08-26 |
Routing methods for use in a logic emulation system
Grant 5,657,241 - Butts , et al. August 12, 1 | 1997-08-12 |
Hardware logic emulation system with memory capability
Grant 5,612,891 - Butts , et al. March 18, 1 | 1997-03-18 |
Hierarchically connected reconfigurable logic assembly
Grant 5,452,231 - Butts , et al. * September 19, 1 | 1995-09-19 |
Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
Grant 5,448,496 - Butts , et al. * September 5, 1 | 1995-09-05 |
Method of using electronically reconfigurable logic circuits
Grant 5,036,473 - Butts , et al. July 30, 1 | 1991-07-30 |
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