loadpatents
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name:-0.011049032211304
name:-0.00047993659973145
Butler; Douglas Blaine Patent Filings

Butler; Douglas Blaine

Patent Applications and Registrations

Patent applications and USPTO patent grants for Butler; Douglas Blaine.The latest application filed is for "twin cell architecture for integrated circuit dynamic random access memory (dram) devices and those devices incorporating embedded dram".

Company Profile
0.10.17
  • Butler; Douglas Blaine - Colorado Springs CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Twin Cell Architecture For Integrated Circuit Dynamic Random Access Memory (dram) Devices And Those Devices Incorporating Embedded Dram
App 20090225613 - Parris; Michael C. ;   et al.
2009-09-10
High-speed, low-power input buffer for integrated circuit devices
Grant 7,583,110 - Butler September 1, 2
2009-09-01
Static Random Access Memory (sram) Compatible, High Availability Memory Array And Method Employing Synchronous Dynamic Random Access Memory (dram) In Conjunction With A Data Cache And Separate Read And Write Registers And Tag Blocks
App 20090106488 - Butler; Douglas Blaine ;   et al.
2009-04-23
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
Grant 7,506,100 - Butler , et al. March 17, 2
2009-03-17
Reduced Area Dynamic Random Access Memory (dram) Cell And Method For Fabricating The Same
App 20080268646 - Butler; Douglas Blaine ;   et al.
2008-10-30
High-speed, Low-power Input Buffer For Integrated Circuit Devices
App 20070176650 - Butler; Douglas Blaine
2007-08-02
High-speed, low-power input buffer for integrated circuit devices
Grant 7,250,795 - Butler July 31, 2
2007-07-31
Shielded Bitline Architecture For Dynamic Random Access Memory (dram) Arrays
App 20070121414 - Butler; Douglas Blaine
2007-05-31
Reduced area dynamic random access memory (DRAM) cell and method for fabricating the same
App 20070085152 - Butler; Douglas Blaine ;   et al.
2007-04-19
Shielded bitline architecture for dynamic random access memory (DRAM) arrays
App 20070058468 - Butler; Douglas Blaine
2007-03-15
High-speed, low-power input buffer for integrated circuit devices
App 20060220704 - Butler; Douglas Blaine
2006-10-05
Dual access DRAM
Grant 7,110,306 - Parris , et al. September 19, 2
2006-09-19
Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM
Grant 7,099,234 - Parris , et al. August 29, 2
2006-08-29
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
App 20060190676 - Butler; Douglas Blaine ;   et al.
2006-08-24
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
App 20060190678 - Butler; Douglas Blaine ;   et al.
2006-08-24
Dual word line mode for DRAMs
Grant 7,002,874 - Parris , et al. February 21, 2
2006-02-21
Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices
App 20060005053 - Jones; Oscar Frederick JR. ;   et al.
2006-01-05
Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM
App 20050286339 - Parris, Michael C. ;   et al.
2005-12-29
Dual access DRAM
App 20050286291 - Parris, Michael C. ;   et al.
2005-12-29
Non-contiguous masked refresh for an integrated circuit memory
Grant 6,912,168 - Parris , et al. June 28, 2
2005-06-28
Integrated circuit transistor body bias regulation circuit and method for low voltage applications
App 20050052219 - Butler, Douglas Blaine ;   et al.
2005-03-10
Bandgap reference circuit
Grant 6,815,941 - Butler November 9, 2
2004-11-09
Non-contiguous masked refresh for an integrated circuit memory
App 20040184334 - Parris, Michael C. ;   et al.
2004-09-23
Bandgap Reference Circuit
App 20040150381 - Butler, Douglas Blaine
2004-08-05
Driver timing and circuit technique for a low noise charge pump circuit
Grant 6,518,829 - Butler February 11, 2
2003-02-11
Driver Timing And Circuit Technique For A Low Noise Charge Pump Circuit
App 20020067201 - Butler, Douglas Blaine
2002-06-06
Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing
Grant 6,337,278 - Butler January 8, 2
2002-01-08

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