Bussa; Vinod

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bussa; Vinod.The latest application filed is for "interrupt migration".

Company Profile

4.11.12

Bussa; Vinod - Hyderabad IN
Bussa; Vinod - Hi-tech city IN
Bussa; Vinod - Hi-tech IN
Bussa; Vinod - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interrupt virtualization Grant 11,188,369 - Arroyo , et al. November 30, 2	2021-11-30
Interrupt Migration App 20210357342 - Schimke; Timothy J. ; et al.	2021-11-18
Processing Data In Memory Using An Fpga App 20210019280 - Lobo; Preetham M. ; et al.	2021-01-21
Interrupt Virtualization App 20200167176 - Arroyo; Jesse ; et al.	2020-05-28
Identifying stale entries in address translation cache Grant 10,261,917 - Bussa , et al.	2019-04-16
Efficient validation of transactional memory in a computer processor Grant 10,169,181 - Bussa , et al. J	2019-01-01
Identifying Stale Entries In Address Translation Cache App 20180121365 - Bussa; Vinod ; et al.	2018-05-03
Efficient Validation Of Transactional Memory In A Computer Processor App 20180074926 - Bussa; Vinod ; et al.	2018-03-15
Identifying stale entries in address translation cache Grant 9,892,060 - Bussa , et al. February 13, 2	2018-02-13
Identifying stale entries in address translation cache Grant 9,720,845 - Bussa , et al. August 1, 2	2017-08-01
Identifying stale entries in address translation cache Grant 9,697,138 - Bussa , et al. July 4, 2	2017-07-04
Identifying Stale Entries In Address Translation Cache App 20170161208 - Bussa; Vinod ; et al.	2017-06-08
Identifying Stale Entries In Address Translation Cache App 20170161209 - Bussa; Vinod ; et al.	2017-06-08
Identifying Stale Entries In Address Translation Cache App 20170161192 - Bussa; Vinod ; et al.	2017-06-08
Identifying stale entries in address translation cache Grant 9,594,680 - Bussa , et al. March 14, 2	2017-03-14
System and method for efficiently testing cache congruence classes during processor design verification and validation Grant 8,019,566 - Bussa , et al. September 13, 2	2011-09-13
Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics Grant 7,966,521 - Bussa , et al. June 21, 2	2011-06-21
System and method for re-shuffling test case instruction orders for processor design verification and validation Grant 7,669,083 - Arora , et al. February 23, 2	2010-02-23
Light Weight And High Throughput Test Case Generation Methodology For Testing Cache/tlb Intervention And Diagnostics App 20100011248 - Bussa; Vinod ; et al.	2010-01-14
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Grant 7,647,539 - Bussa , et al. January 12, 2	2010-01-12
System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation App 20090070631 - Arora; Sampan ; et al.	2009-03-12
System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation App 20090070532 - Bussa; Vinod ; et al.	2009-03-12
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation App 20090024892 - Bussa; Vinod ; et al.	2009-01-22

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