Burlison; Phillip D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Burlison; Phillip D..The latest application filed is for "methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test".

Company Profile

0.11.2

Burlison; Phillip D. - Morgan Hill CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test Grant 8,127,186 - Burlison , et al. February 28, 2	2012-02-28
System and method for device performance characterization in physical and logical domains with AC SCAN testing Grant 8,006,149 - Dokken , et al. August 23, 2	2011-08-23
Dynamic mask memory for serial scan testing Grant 7,865,788 - Burlison , et al. January 4, 2	2011-01-04
Apparatus for locating a defect in a scan chain while testing digital logic Grant 7,650,547 - Burlison , et al. January 19, 2	2010-01-19
Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test App 20080215940 - Burlison; Phillip D. ; et al.	2008-09-04
System and Method for Device Performance Characterization in Physical and Logical Domains with AC SCAN Testing App 20080126896 - Dokken; Richard C. ; et al.	2008-05-29
Dynamically reconfigurable precision signal delay test system for automatic test equipment Grant 7,114,114 - Burlison , et al. September 26, 2	2006-09-26
System for dynamic re-allocation of test pattern data for parallel and serial test data patterns Grant 7,032,145 - Burlison April 18, 2	2006-04-18
Dynamically reconfigurable precision signal delay test system for automatic test equipment Grant 7,013,417 - Burlison , et al. March 14, 2	2006-03-14
Dynamically reconfigurable precision signal delay test system for automatic test equipment Grant 6,880,137 - Burlison , et al. April 12, 2	2005-04-12
High speed I.sub.DDQ monitor circuit Grant 5,694,063 - Burlison , et al. December 2, 1	1997-12-02
High speed I.sub.DDQ monitor circuit Grant 5,552,744 - Burlison , et al. September 3, 1	1996-09-03
Test system apparatus with Schottky diodes with programmable voltages Grant 5,200,696 - Menis , et al. April 6, 1	1993-04-06

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