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Patent applications and USPTO patent grants for Bures; Edmond R..The latest application filed is for "testing a hardware emulation model of a circuit with software checker routines designed for an rtl model of the circuit".
Patent | Date |
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Automatically identifying resettable flops for digital designs Grant 8,869,080 - Bures , et al. October 21, 2 | 2014-10-21 |
Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit App 20140100841 - Bures; Edmond R. ;   et al. | 2014-04-10 |
Automatically Identifying Resettable Flops For Digital Designs App 20140089873 - Bures; Edmond R. ;   et al. | 2014-03-27 |
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