Burek; Dwayne
Patent Applications and Registrations
Patent applications and USPTO patent grants for Burek; Dwayne.The latest application filed is for "method and program product for designing hierarchical circuit for quiescent current testing".
- Burek; Dwayne - San Jose CA
| Patent | Date |
|---|---|
| Method and program product for designing hierarchical circuit for quiescent current testing Grant 6,862,717 - Nadeau-Dostie , et al. March 1, 2 | 2005-03-01 |
| Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby Grant 6,615,392 - Nadeau-Dostie , et al. September 2, 2 | 2003-09-02 |
| Method and program product for designing hierarchical circuit for quiescent current testing App 20030115522 - Nadeau-Dostie, Benoit ; et al. | 2003-06-19 |
| Method and apparatus for testing high performance circuits Grant 6,510,534 - Nadeau-Dostie , et al. January 21, 2 | 2003-01-21 |
| Method And Program Product For Modeling Circuits With Latch Based Design App 20020143515 - Nadeau-Dostie, Benoit ; et al. | 2002-10-03 |
| Method and program product for modeling circuits with latch based design Grant 6,457,161 - Nadeau-Dostie , et al. September 24, 2 | 2002-09-24 |
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