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name:-0.026610136032104
name:-0.011234998703003
name:-0.00051498413085938
Burbach; Gert Patent Filings

Burbach; Gert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Burbach; Gert.The latest application filed is for "temperature monitoring in a semiconductor device by using a pn junction based on silicon/germanium materials".

Company Profile
0.13.17
  • Burbach; Gert - Dresden DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials
Grant 8,796,807 - Stephan , et al. August 5, 2
2014-08-05
Temperature Monitoring In A Semiconductor Device By Using A Pn Junction Based On Silicon/germanium Materials
App 20120025276 - Stephan; Rolf ;   et al.
2012-02-02
Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
Grant 7,732,291 - Bloomquist , et al. June 8, 2
2010-06-08
Temperature Monitoring In A Semiconductor Device By Using An Pn Junction Based On Silicon/germanium Material
App 20090218601 - Stephan; Rolf ;   et al.
2009-09-03
Technique for forming a strained transistor by a late amorphization and disposable spacers
Grant 7,354,836 - Hoentschel , et al. April 8, 2
2008-04-08
Gate structure and a transistor having asymmetric spacer elements and methods of forming the same
Grant 7,354,839 - Wei , et al. April 8, 2
2008-04-08
A Semiconductor Device Having Stressed Etch Stop Layers Of Different Intrinsic Stress In Combination With Pn Junctions Of Different Design In Different Device Regions
App 20070254444 - Bloomquist; Joe ;   et al.
2007-11-01
Method Of Forming A Semiconductor Structure Comprising Transistor Elements With Differently Stressed Channel Regions
App 20070207583 - Burbach; Gert ;   et al.
2007-09-06
Technique For Forming A Strained Transistor By A Late Amorphization And Disposable Spacers
App 20070202653 - Hoentschel; Jan ;   et al.
2007-08-30
Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions
Grant 7,238,578 - Burbach , et al. July 3, 2
2007-07-03
Gate structure and a transistor having asymmetric spacer elements and methods of forming the same
App 20060194381 - Wei; Andy ;   et al.
2006-08-31
Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions
App 20060046400 - Burbach; Gert ;   et al.
2006-03-02
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer
Grant 7,005,380 - Aminpur , et al. February 28, 2
2006-02-28
Technique for evaluating local electrical characteristics in semiconductor devices
App 20060022197 - Wirbeleit; Frank ;   et al.
2006-02-02
Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding
Grant 6,943,088 - van Bentum , et al. September 13, 2
2005-09-13
Diode structure for SOI circuits
Grant 6,905,924 - Burbach , et al. June 14, 2
2005-06-14
Method of forming local interconnect barrier layers
App 20050101120 - Hause, Fred ;   et al.
2005-05-12
Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area
Grant 6,821,840 - Wieczorek , et al. November 23, 2
2004-11-23
SOI field effect transistor element having an ohmic substrate contact
App 20040217421 - Aminpur, Massud ;   et al.
2004-11-04
Diode structure for SOI circuits
App 20040188768 - Burbach, Gert ;   et al.
2004-09-30
Trench isolation structure for a semiconductor device with a different degree of corner rounding and a method of manufacturing the same
App 20040119135 - van Bentum, Ralf ;   et al.
2004-06-24
Simultaneous formation of device and backside contacts on wafers having a buried insulator layer
App 20040121599 - Aminpur, Massud ;   et al.
2004-06-24
Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer
Grant 6,720,242 - Burbach , et al. April 13, 2
2004-04-13
Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area
App 20040043558 - Wieczorek, Karsten ;   et al.
2004-03-04
Semiconductor device having an improved local interconnect structure and a method for forming such a device
Grant 6,656,825 - Burbach December 2, 2
2003-12-02
Semiconductor Device Having An Improved Local Interconnect Structure And A Method For Forming Such A Device
App 20030201490 - Burbach, Gert
2003-10-30
SOI transistor element having an improved backside contact and method of forming the same
App 20030203546 - Burbach, Gert ;   et al.
2003-10-30
Semiconductor device having a reduced signal processing time and a method of fabricating the same
Grant 6,541,863 - Horstmann , et al. April 1, 2
2003-04-01
Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer
App 20020055244 - Burbach, Gert ;   et al.
2002-05-09

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