Bull HN Information Systems Italia S.p.A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bull HN Information Systems Italia S.p.A..The latest application filed is for "data-processing system with cc-numa (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory".

Company Profile

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Bull HN Information Systems Italia S.p.A. - Turin IT
Bull HN Information Systems Italia S.P.A. - Milan IT
Bull HN Information Systems Italia S.p.A. - Pregnana Milanese IT
Bull HN Information Systems Italia S.p.A. - IT IT
Bull HN Information Systems Italia S.P.A. - Caluso-Turin IT
Bull HN Information Systems Italia S.p.A. - Torino IT
Bull HN Information Systems Italia S.p.A. - Caluso IT
Bull HN Information Systems Italia S.p.A. - N/A
Bull HN Information Systems Italia S.p.A. - Billerica MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data-processing system with CC-NUMA (cache-coherent, non-uniform memory access) architecture and remote cache incorporated in local memory Grant 6,243,794 - Casamatta June 5, 2	2001-06-05
Interface bridge between a system bus and local buses with translation of local addresses for system space access programmable by address space Grant 6,173,383 - Casamatta January 9, 2	2001-01-09
Dynamic random access memory (DRAM) having variable configuration for data processing system and corresponding expansion support for the interleaved-block configuration thereof Grant 6,170,035 - Gianellini , et al. January 2, 2	2001-01-02
Unit for arbitration of access to a bus of a multiprocessor system with multiprocessor system for access to a plurality of shared resources, with temporary masking of pseudo random duration of access requests for the execution of access retry Grant 5,941,967 - Zulian August 24, 1	1999-08-24
Power supply with power factor correction and protection against failures of the power factor correction Grant 5,617,013 - Cozzi April 1, 1	1997-04-01
Computer frame of riveted modular construction Grant 5,590,938 - De Andrea January 7, 1	1997-01-07
Digital information error correcting apparatus for single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC) Grant 5,535,227 - Silvano July 9, 1	1996-07-09
Electrophotographic apparatus incorporating offset stacking Grant 5,512,996 - Fare April 30, 1	1996-04-30
Method for debugging and testing the correctness of programs Grant 5,319,645 - Bassi , et al. June 7, 1	1994-06-07
Multiprocessor system having distributed shared resources and dynamic and selective global data replication Grant 5,274,789 - Costa , et al. December 28, 1	1993-12-28
Centralized arbitration system using the status of target resources to selectively mask requests from master units Grant 5,253,347 - Bagnoli , et al. October 12, 1	1993-10-12
Multiprocessor system with global data replication and two levels of address translation units Grant 5,247,629 - Casamatta , et al. September 21, 1	1993-09-21
Multiprocessor system having distributed shared resources and dynamic global data replication Grant 5,247,673 - Costa , et al. September 21, 1	1993-09-21
Multiprocessor system having global data replication Grant 5,214,776 - Bagnoli , et al. May 25, 1	1993-05-25
TTL technology digital timing unit Grant 4,951,301 - Zulian August 21, 1	1990-08-21
Multiprocessor system featuring global data multiplation Grant 4,928,224 - Zulian May 22, 1	1990-05-22
Hit predictive cache memory Grant 4,912,626 - Fiacconi March 27, 1	1990-03-27
Transparent cache memory Grant 4,872,138 - Ciacci October 3, 1	1989-10-03
Fault tolerant computer architecture Grant 4,849,979 - Maccianti , et al. July 18, 1	1989-07-18

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