Buehler; Markus

Patent Applications and Registrations

Patent applications and USPTO patent grants for Buehler; Markus.The latest application filed is for "partial computer processor core shutoff".

Company Profile

2.27.26

Buehler; Markus - Schoenbuch DE
Buehler; Markus - Weil im Schoenbuch DE
Buehler; Markus - Boeblingen N/A DE
Buehler; Markus - Sindelfingen DE
Buehler; Markus - Schonbuch DE
Buehler; Markus - Wei im Schoenbuch DE
Buehler; Markus - Weil im Shoenbuch DE
Buehler; Markus - 71093 Weil im Schoenbuch DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Partial computer processor core shutoff Grant 11,281,474 - Maurer , et al. March 22, 2	2022-03-22
Partial Computer Processor Core Shutoff App 20210303313 - Maurer; Thilo ; et al.	2021-09-30
Hardware apparatus to measure memory locality Grant 10,831,493 - Buehler , et al. November 10, 2	2020-11-10
Hardware Apparatus To Measure Memory Locality App 20200192669 - BUEHLER; Markus ; et al.	2020-06-18
Congestion mitigation by wire ordering Grant 9,760,669 - Buehler , et al. September 12, 2	2017-09-12
Congestion Mitigation By Wire Ordering App 20170132351 - Buehler; Markus ; et al.	2017-05-11
Parsing data representative of a hardware design into commands of a hardware design environment Grant 8,756,538 - Anderson , et al. June 17, 2	2014-06-17
Method and system for calculating timing delay in a repeater network in an electronic circuit Grant 8,731,858 - Buehler , et al. May 20, 2	2014-05-20
Gate configuration determination and selection from standard cell library Grant 8,627,263 - Buechner , et al. January 7, 2	2014-01-07
Estimating power consumption of an electronic circuit Grant 8,612,911 - Buechner , et al. December 17, 2	2013-12-17
Parsing Data Representative of a Hardware Design into Commands of a Hardware Design Environment App 20130219150 - Anderson; Hans-Werner ; et al.	2013-08-22
Signal repowering chip for 3-dimensional integrated circuit Grant 8,513,663 - Buehler , et al. August 20, 2	2013-08-20
Write buffer for improved DRAM write access patterns Grant 8,495,286 - Balkesen , et al. July 23, 2	2013-07-23
Glitch power reduction Grant 8,407,654 - Buechner , et al. March 26, 2	2013-03-26
Glitch Power Reduction App 20120266120 - Buechner; Thomas ; et al.	2012-10-18
Estimating Power Consumption Of An Electronic Circuit App 20120216160 - Buechner; Thomas ; et al.	2012-08-23
Gate Configuration Determination And Selection From Standard Cell Library App 20120216168 - Buechner; Thomas ; et al.	2012-08-23
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 8,234,594 - Anderson , et al. July 31, 2	2012-07-31
Write Buffer for Improved DRAM Write Access Patterns App 20110302367 - Balkesen; Cagri ; et al.	2011-12-08
Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit Grant 8,032,851 - Belaidi , et al. October 4, 2	2011-10-04
Routing of wires of an electronic circuit Grant 8,015,527 - Buehler , et al. September 6, 2	2011-09-06
Method and system for placement of electric circuit components in integrated circuit design Grant 8,010,925 - Buehler , et al. August 30, 2	2011-08-30
Test yield estimate for semiconductor products created from a library Grant 8,010,916 - Bickford , et al. August 30, 2	2011-08-30
Reducing coupling between wires of an electronic circuit Grant 8,006,208 - Belaidi , et al. August 23, 2	2011-08-23
Computer readable medium, system and associated method for designing integrated circuits with loop insertions Grant 7,996,808 - Arp , et al. August 9, 2	2011-08-09
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,984,394 - Anderson , et al. July 19, 2	2011-07-19
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,960,836 - Anderson , et al. June 14, 2	2011-06-14
Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing Grant 7,904,861 - Buehler , et al. March 8, 2	2011-03-08
Post-routing Coupling Fixes For Integrated Circuits App 20100257503 - Buehler; Markus ; et al.	2010-10-07
Signal Repowering Chip For 3-Dimensional Integrated Circuit App 20100237700 - Buehler; Markus ; et al.	2010-09-23
Reducing Coupling Between Wires Of An Electronic Circuit App 20100223588 - Belaidi; Moussadek ; et al.	2010-09-02
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20100211923 - Anderson; Brent A. ; et al.	2010-08-19
Method and System for Calculating Timing Delay in a Repeater Network in an Electronic Circuit App 20100100347 - Buehler; Markus ; et al.	2010-04-22
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20090158231 - Anderson; Brent A. ; et al.	2009-06-18
Computer Readable Medium, System and Associated Method For Designing Integrated Circuits With Loop Insertions App 20090031274 - Arp; Andreas ; et al.	2009-01-29
Delay Calculation Method, A Data Processing Program and A Computer Program Product for Routing of Wires of an Electronic Circuit App 20090013293 - Buehler; Markus ; et al.	2009-01-08
Method, System, And Computer Program Product For Coupled Noise Timing Violation Avoidance In Detailed Routing App 20080313588 - Buehler; Markus ; et al.	2008-12-18
Method and System for Placement of Electric Circuit Components in Integrated Circuit Design App 20080301612 - Buehler; Markus ; et al.	2008-12-04
Test Yield Estimate For Semiconductor Products Created From A Library App 20080189664 - Bickford; Jeanne ; et al.	2008-08-07
Integrated Circuit Design For Reducing Coupling Between Wires Of An Electronic Circuit App 20080184186 - Belaidi; Moussadek ; et al.	2008-07-31
Redundant Micro-loop Structure For Use In An Intergrated Circuit Physical Design Process And Method Of Forming The Same App 20080150149 - Anderson; Brent A. ; et al.	2008-06-26
Routing Method For Reducing Coupling Between Wires Of An Electronic Circuit App 20080148213 - Belaidi; Moussadek ; et al.	2008-06-19
Test yield estimate for semiconductor products created from a library Grant 7,386,815 - Bickford , et al. June 10, 2	2008-06-10
Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process And Method Of Forming The Same App 20080097738 - Anderson; Brent A. ; et al.	2008-04-24
Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated Circuit App 20080059933 - Barke; Erich ; et al.	2008-03-06
Test Yield Estimate For Semiconductor Products Created From A Library App 20070099236 - Bickford; Jeanne ; et al.	2007-05-03
Method for placement of pipeline latches App 20060136854 - Arp; Andreas ; et al.	2006-06-22

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