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System and method for memory migration in distributed-memory multi-processor systems
Grant 7,103,728 - Sharma , et al. September 5, 2 | 2006-09-05 |
System and method for memory interleaving using cell map with entry grouping for higher-way interleaving
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Forming linked lists using content addressable memory
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System and method for memory migration in distributed-memory multi-processor systems
App 20040019751 - Sharma, Debendra Das ; et al. | 2004-01-29 |
System and method for memory interleaving using cell map with entry grouping for higher-way interleaving
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Apparatus and method for a virtual hashed page table
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Method and apparatus for calculating a page table index from a virtual address
Grant 6,393,544 - Bryg , et al. May 21, 2 | 2002-05-21 |
Queue-based predictive flow control mechanism with indirect determination of queue fullness
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Method and apparatus for pre-validating regions in a virtual addressing scheme
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Method and apparatus for transferring data in a computer system
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Method and apparatus for ensuring data consistency between an i/o channel and a processor
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Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address
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Method and apparatus for checking cache coherency in a computer architecture
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Software and hardware-managed translation lookaside buffer
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Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer
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Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
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Partial cache line write transactions in a computing system with a write back cache
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Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
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Fast pipelined distributed arbitration scheme
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Flexible N-way memory interleaving
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Software method for implementing dismissible instructions on a computer
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Explicit instructions for control of translation lookaside buffers
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Cache tag lookaside
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Privilege level checking instruction for implementing a secure hierarchical computer system
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Direct input/output in a virtual memory system
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Method and means for moving bytes in a reduced instruction set computer
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Cache memory consistency control with explicit software instructions
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