loadpatents
Patent applications and USPTO patent grants for Brunolli; Michael.The latest application filed is for "composite embedded voltage regulator (cevr)".
Patent | Date |
---|---|
Memory interface with adjustable voltage and termination and methods of use Grant 10,613,613 - Brunolli , et al. | 2020-04-07 |
Composite embedded voltage regulator (CEVR) Grant 10,461,643 - Brunolli Oc | 2019-10-29 |
Composite Embedded Voltage Regulator (cevr) App 20190312515 - Brunolli; Michael | 2019-10-10 |
Low-power clocking for a high-speed memory interface Grant 10,169,262 - West , et al. J | 2019-01-01 |
Layout Construction For Addressing Electromigration App 20180211957 - RASOULI; Seid Hadi ;   et al. | 2018-07-26 |
Memory Interface With Adjustable Voltage And Termination And Methods Of Use App 20180129267 - BRUNOLLI; Michael ;   et al. | 2018-05-10 |
Memory interface with adjustable voltage and termination and methods of use Grant 9,910,482 - Brunolli , et al. March 6, 2 | 2018-03-06 |
Method and apparatus for routing die signals using external interconnects Grant 9,871,012 - Srinivas , et al. January 16, 2 | 2018-01-16 |
Memory Interface With Adjustable Voltage And Termination And Methods Of Use App 20170090546 - Brunolli; Michael ;   et al. | 2017-03-30 |
Low-power Clocking For A High-speed Memory Interface App 20170017587 - West; David ;   et al. | 2017-01-19 |
Electrostatic discharge clamp with disable Grant 9,083,176 - Worley , et al. July 14, 2 | 2015-07-14 |
Output Driver With Slew Rate Calibration App 20150109023 - Brunolli; Michael ;   et al. | 2015-04-23 |
Calibrated Output Driver With Enhanced Reliability And Density App 20150109030 - Brunolli; Michael ;   et al. | 2015-04-23 |
Passing High Voltage Inputs Using A Controlled Floating Pass Gate App 20150042401 - Knol; Stephen ;   et al. | 2015-02-12 |
Area and power saving standard cell methodology Grant 8,893,063 - Malek-Khosravi , et al. November 18, 2 | 2014-11-18 |
Electrostatic Discharge Clamp With Disable App 20140198414 - Worley; Eugene Robert ;   et al. | 2014-07-17 |
Method And Apparatus For Routing Die Signals Using External Interconnects App 20140061642 - Srinivas; Vaishnav ;   et al. | 2014-03-06 |
Area And Power Saving Standard Cell Methodology App 20130214380 - Malek-Khosravi; Behnam ;   et al. | 2013-08-22 |
Area and power saving standard cell methodology Grant 8,423,930 - Malek-Khosravi , et al. April 16, 2 | 2013-04-16 |
Area and power saving standard cell methodology Grant 7,802,216 - Malek-Khosravi , et al. September 21, 2 | 2010-09-21 |
Area And Power Saving Standard Cell Methodology App 20100188060 - Malek-Khosravi; Behnam ;   et al. | 2010-07-29 |
Area And Power Saving Standard Cell Methodology App 20090077514 - Malek-Khosravi; Behnam ;   et al. | 2009-03-19 |
Digitally switched impedance having improved linearity and settling time Grant 6,384,762 - Brunolli , et al. May 7, 2 | 2002-05-07 |
Digitally switched impedance having improved linearity and settling time App 20010038351 - Brunolli, Michael ;   et al. | 2001-11-08 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.