Bruce; Ricardo H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bruce; Ricardo H..The latest application filed is for "multilevel memory bus system".

Company Profile

6.31.8

Bruce; Ricardo H. - Fremont CA
Bruce; Ricardo H. - Union City CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multilevel memory bus system Grant 10,877,907 - Bruce , et al. December 29, 2	2020-12-29
Multi-dimensional computer storage system Grant 10,552,050 - Verdan , et al. Fe	2020-02-04
Scatter-gather approach for parallel data transfer in a mass storage system Grant 10,489,318 - Bruce , et al. Nov	2019-11-26
Data storage system with configurable prefetch buffers Grant 10,459,842 - Bruce , et al. Oc	2019-10-29
Bus arbitration with routing and failover mechanism Grant 10,430,303 - Bruce , et al. O	2019-10-01
Bus arbitration with routing and failover mechanism Grant 10,423,554 - Bruce , et al. Sept	2019-09-24
Multilevel Memory Bus System App 20190087363 - Bruce; Ricardo H. ; et al.	2019-03-21
Multilevel memory bus system Grant 10,133,686 - Bruce , et al. November 20, 2	2018-11-20
Memory transaction with reduced latency Grant 10,120,586 - Bruce , et al. November 6, 2	2018-11-06
Multi-level message passing descriptor Grant 10,013,373 - Bruce , et al. July 3, 2	2018-07-03
Scatter-gather approach for parallel data transfer in a mass storage system Grant 9,971,524 - Bruce , et al. May 15, 2	2018-05-15
Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation Grant 9,952,991 - Bruce , et al. April 24, 2	2018-04-24
Bus arbitration with routing and failover mechanism Grant 9,916,213 - Bruce , et al. March 13, 2	2018-03-13
Network of memory systems Grant 9,875,205 - Bruce , et al. January 23, 2	2018-01-23
Bus arbitration with routing and failover mechanism Grant 9,798,688 - Bruce , et al. October 24, 2	2017-10-24
Multi-level message passing descriptor Grant 9,501,436 - Bruce , et al. November 22, 2	2016-11-22
Multi-profile memory controller for computing devices Grant 9,135,190 - Bruce , et al. September 15, 2	2015-09-15
Reduced latency memory read transactions in storage devices Grant 8,959,307 - Bruce , et al. February 17, 2	2015-02-17
Multilevel Memory Bus System App 20140289441 - Bruce; Ricardo H. ; et al.	2014-09-25
Multilevel memory bus system for solid-state mass storage Grant 8,788,725 - Bruce , et al. July 22, 2	2014-07-22
Multilevel Memory Bus System For Solid-State Mass Storage App 20130246694 - Bruce; Ricardo H. ; et al.	2013-09-19
Multilevel memory bus system for solid-state mass storage Grant 8,447,908 - Bruce , et al. May 21, 2	2013-05-21
Multiple chip module and package stacking method for storage devices Grant 8,093,103 - Bruce , et al. January 10, 2	2012-01-10
Multilevel Memory Bus System For Solid-state Mass Storage App 20110161568 - Bruce; Ricardo H. ; et al.	2011-06-30
Apparatus for networking devices having fibre channel node functionality Grant 7,729,370 - Orcine , et al. June 1, 2	2010-06-01
Network storage device having solid-state non-volatile memory Grant 6,981,070 - Luk , et al. December 27, 2	2005-12-27
Method and apparatus for data recovery Grant 6,970,890 - Bruce , et al. November 29, 2	2005-11-29
Parallel erase operations in memory systems Grant 6,529,416 - Bruce , et al. March 4, 2	2003-03-04
Method and system for controlling data in a computer system in the event of a power failure Grant 6,496,939 - Portman , et al. December 17, 2	2002-12-17
Parallel erase operations in memory systems App 20020141244 - Bruce, Ricardo H. ; et al.	2002-10-03
Parallel Erase Operations In Memory Systems App 20020097594 - Bruce, Ricardo H. ; et al.	2002-07-25
Method And System For Controlling Data In A Computer System App 20020049917 - PORTMAN, ROLAND F. ; et al.	2002-04-25
Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage Grant 6,000,006 - Bruce , et al. December 7, 1	1999-12-07
Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations Grant 5,956,743 - Bruce , et al. September 21, 1	1999-09-21
Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers Grant 5,822,251 - Bruce , et al. October 13, 1	1998-10-13

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