loadpatents
name:-0.037783861160278
name:-0.024935960769653
name:-0.0046889781951904
Brown; Mary D. Patent Filings

Brown; Mary D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Brown; Mary D..The latest application filed is for "thread transition management".

Company Profile
4.26.27
  • Brown; Mary D. - Austin TX
  • Brown; Mary D - Austin TX
  • Brown; Mary D. - Ausin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Thread transition management
Grant 11,256,507 - Abernathy , et al. February 22, 2
2022-02-22
Thread Transition Management
App 20190250918 - Abernathy; Christopher M. ;   et al.
2019-08-15
Processor For Avoiding Reduced Performance Using Instruction Metadata To Determine Not To Maintain A Mapping Of A Logical Regist
App 20190250913 - Abernathy; Christopher M ;   et al.
2019-08-15
Thread transition management
Grant 10,296,339 - Abernathy , et al.
2019-05-21
Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
Grant 10,275,251 - Abernathy , et al.
2019-04-30
Thread Transition Management
App 20180349141 - Abernathy; Christopher M. ;   et al.
2018-12-06
Thread transition management
Grant 10,055,226 - Abernathy , et al. August 21, 2
2018-08-21
Methods for core recovery after a cold start
Grant 10,007,616 - Feero , et al. June 26, 2
2018-06-26
Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers
Grant 9,959,121 - Abernathy , et al. May 1, 2
2018-05-01
Thread Transition Management
App 20170300331 - Abernathy; Christopher M. ;   et al.
2017-10-19
Thread transition management
Grant 9,703,561 - Abernathy , et al. July 11, 2
2017-07-11
Efficient Usage Of A Multi-level Register File Utilizing A Register File Bypass
App 20160154650 - Abernathy; Christopher M. ;   et al.
2016-06-02
Efficient usage of a multi-level register file utilizing a register file bypass
Grant 9,286,068 - Abernathy , et al. March 15, 2
2016-03-15
Thread Transition Management
App 20140258691 - Abernathy; Christopher M. ;   et al.
2014-09-11
Thread transition management
Grant 8,725,993 - Abernathy , et al. May 13, 2
2014-05-13
Efficient Usage Of A Register File Mapper And First-level Data Register File
App 20140122841 - Abernathy; Christopher M. ;   et al.
2014-05-01
Efficient Usage Of A Register File Mapper Mapping Structure
App 20140122842 - Abernathy; Christopher M. ;   et al.
2014-05-01
Efficient Usage Of A Multi-level Register File Utilizing A Register File Bypass
App 20140122840 - Abernathy; Christopher M. ;   et al.
2014-05-01
Multi-level register file supporting multiple threads
Grant 8,661,227 - Abernathy , et al. February 25, 2
2014-02-25
Multi-level register file supporting multiple threads
Grant 8,661,228 - Abernathy , et al. February 25, 2
2014-02-25
Register file supporting transactional processing
Grant 8,631,223 - Abernathy , et al. January 14, 2
2014-01-14
Thread Transition Management
App 20120216004 - Abernathy; Christopher M. ;   et al.
2012-08-23
Multi-level Register File Supporting Multiple Threads
App 20120204009 - ABERNATHY; CHRISTOPHER M. ;   et al.
2012-08-09
System and method for double-issue instructions using a dependency matrix
Grant 8,239,661 - Abernathy , et al. August 7, 2
2012-08-07
Multi-level Register File Supporting Multiple Threads
App 20120072700 - ABERNATHY; CHRISTOPHER M. ;   et al.
2012-03-22
System and method for double-issue instructions using a dependency matrix and a side issue queue
Grant 8,135,942 - Abernathy , et al. March 13, 2
2012-03-13
Dependency matrix with reduced area and power consumption
Grant 8,127,116 - Islam , et al. February 28, 2
2012-02-28
Tracking deallocated load instructions using a dependence matrix
Grant 8,099,582 - Abernathy , et al. January 17, 2
2012-01-17
Structure for implementing speculative clock gating of digital logic circuits
Grant 8,078,999 - Blaner , et al. December 13, 2
2011-12-13
Register File Supporting Transactional Processing
App 20110283096 - ABERNATHY; CHRISTOPHER M. ;   et al.
2011-11-17
Issuing instructions in-order in an out-of-order processor using false dependencies
Grant 8,037,366 - Abernathy , et al. October 11, 2
2011-10-11
Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system
Grant 7,991,979 - Abernathy , et al. August 2, 2
2011-08-02
Apparatus and method for implementing speculative clock gating of digital logic circuits
Grant 7,971,161 - Blaner , et al. June 28, 2
2011-06-28
Detecting and Handling Short Forward Branch Conversion Candidates
App 20100262813 - Brown; Mary D. ;   et al.
2010-10-14
Dependency Matrix with Improved Performance
App 20100257339 - Brown; Mary D. ;   et al.
2010-10-07
Selective Execution Dependency Matrix
App 20100257341 - Brown; Mary D. ;   et al.
2010-10-07
Dependency Matrix with Reduced Area and Power Consumption
App 20100257336 - Islam; Saiful ;   et al.
2010-10-07
Tracking Deallocated Load Instructions Using a Dependence Matrix
App 20100250902 - Abernathy; Christopher M. ;   et al.
2010-09-30
Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies
App 20100251016 - Abernathy; Christopher M. ;   et al.
2010-09-30
Method and system for restoring register mapper states for an out-of-order microprocessor
Grant 7,689,812 - Abernathy , et al. March 30, 2
2010-03-30
System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System
App 20100077181 - Abernathy; Christopher M. ;   et al.
2010-03-25
System and Method for Double-Issue Instructions Using a Dependency Matrix
App 20100058035 - Abernathy; Christopher M. ;   et al.
2010-03-04
System and Method for Double-Issue Instructions Using a Dependency Matrix and a Side Issue Queue
App 20100058033 - Abernathy; Christopher M. ;   et al.
2010-03-04
Apparatus And Method For Implementing Speculative Clock Gating Of Digital Logic Circuits
App 20090193281 - Blaner; Bartholomew ;   et al.
2009-07-30
Design Structure For Implementing Speculative Clock Gating Of Digital Logic Circuits
App 20090193283 - Blaner; Bartholomew ;   et al.
2009-07-30
System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit
App 20090113182 - Abernathy; Christopher M. ;   et al.
2009-04-30
Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor
App 20080195850 - Abernathy; Christopher M. ;   et al.
2008-08-14
Select-free dynamic instruction scheduling
Grant 6,988,185 - Stark, IV , et al. January 17, 2
2006-01-17
Select-free dynamic instruction scheduling
App 20030140216 - Stark, Jared W. IV ;   et al.
2003-07-24

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