Bron; Michel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bron; Michel.The latest application filed is for "integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same".

Company Profile

0.13.9

Bron; Michel - Lausanne N/A CH

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same Grant 8,395,937 - Fisch , et al. March 12, 2	2013-03-12
Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same App 20110249499 - Fisch; David ; et al.	2011-10-13
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same Grant 7,969,779 - Fisch , et al. June 28, 2	2011-06-28
Semiconductor memory device and method of operating same Grant 7,733,693 - Ferrant , et al. June 8, 2	2010-06-08
Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same App 20090231898 - Fisch; David ; et al.	2009-09-17
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same Grant 7,542,340 - Fisch , et al. June 2, 2	2009-06-02
Semiconductor memory device and method of operating same App 20080205114 - Ferrant; Richard ; et al.	2008-08-28
Semiconductor memory device and method of operating same Grant 7,359,229 - Ferrant , et al. April 15, 2	2008-04-15
Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same App 20080013359 - Fisch; David ; et al.	2008-01-17
Semiconductor memory device and method of operating same App 20070159911 - Ferrant; Richard ; et al.	2007-07-12
Semiconductor memory device and method of operating same Grant 7,187,581 - Ferrant , et al. March 6, 2	2007-03-06
Semiconductor memory cell, array, architecture and device, and method of operating same Grant 7,085,153 - Ferrant , et al. August 1, 2	2006-08-01
Semiconductor memory device and method of operating same Grant 7,085,156 - Ferrant , et al. August 1, 2	2006-08-01
Semiconductor memory device and method of operating same App 20050174873 - Ferrant, Richard ; et al.	2005-08-11
Semiconductor memory device and method of operating same App 20050157580 - Ferrant, Richard ; et al.	2005-07-21
Semiconductor memory cell, array, architecture and device, and method of operating same App 20050013163 - Ferrant, Richard ; et al.	2005-01-20
Semiconductor memory device and method of operating same App 20040228168 - Ferrant, Richard ; et al.	2004-11-18
Method and apparatus for writing an erasable non-volatile memory Grant 6,128,224 - Morton , et al. October 3, 2	2000-10-03
Protection circuit for a microprocessor Grant 5,557,743 - Pombo , et al. September 17, 1	1996-09-17
Memory cards Grant 4,910,393 - Gercekci , et al. March 20, 1	1990-03-20
Data card circuits Grant 4,841,133 - Gercekci , et al. June 20, 1	1989-06-20

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