Brofman; Peter J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Brofman; Peter J..The latest application filed is for "low-stress dual underfill packaging".

Company Profile

0.27.16

Brofman; Peter J. - Hopewell Junction NY
Brofman; Peter J - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low-stress dual underfill packaging Grant 9,698,072 - Brofman , et al. July 4, 2	2017-07-04
Low-stress dual underfill packaging Grant 9,373,559 - Brofman , et al. June 21, 2	2016-06-21
Low-stress Dual Underfill Packaging App 20160049345 - Brofman; Peter J. ; et al.	2016-02-18
Low-stress Dual Underfill Packaging App 20150255312 - Brofman; Peter J. ; et al.	2015-09-10
Flip chip assembly apparatus employing a warpage-suppressor assembly Grant 8,978,960 - Brofman , et al. March 17, 2	2015-03-17
Additives for grain fragmentation in Pb-free Sn-based solder Grant 8,910,853 - Arvin , et al. December 16, 2	2014-12-16
Flip chip assembly apparatus employing a warpage-suppressor assembly Grant 8,870,051 - Brofman , et al. October 28, 2	2014-10-28
Flip Chip Assembly Apparatus Employing A Warpage-suppressor Assembly App 20140124566 - Brofman; Peter J. ; et al.	2014-05-08
Flip Chip Assembly Apparatus Employing A Warpage-suppressor Assembly App 20130292455 - Brofman; Peter J. ; et al.	2013-11-07
ADDITIVES FOR GRAIN FRAGMENTATION IN Pb-FREE Sn-BASED SOLDER App 20130284495 - Arvin; Charles L. ; et al.	2013-10-31
Additives for grain fragmentation in Pb-free Sn-based solder Grant 8,493,746 - Arvin , et al. July 23, 2	2013-07-23
Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners Grant 7,875,502 - Brofman , et al. January 25, 2	2011-01-25
Semiconductor Chips With Crack Stop Regions For Reducing Crack Propagation From Chip Edges/corners App 20100233872 - Brofman; Peter J. ; et al.	2010-09-16
ADDITIVES FOR GRAIN FRAGMENTATION IN Pb-FREE Sn-BASED SOLDER App 20100200271 - Arvin; Charles L. ; et al.	2010-08-12
Lid edge capping load Grant 7,733,655 - Beaumier , et al. June 8, 2	2010-06-08
Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners Grant 7,732,932 - Brofman , et al. June 8, 2	2010-06-08
Thermal pillow Grant 7,709,951 - Brodsky , et al. May 4, 2	2010-05-04
Lid Edge Capping Load App 20100020503 - BEAUMIER; MARTIN ; et al.	2010-01-28
Semiconductor Chips With Crack Stop Regions For Reducing Crack Propagation From Chip Edges/corners App 20090032909 - Brofman; Peter J. ; et al.	2009-02-05
Thermal Pillow App 20080225484 - Brodsky; William L. ; et al.	2008-09-18
Dielectric interposer for chip to substrate soldering Grant 6,984,792 - Brofman , et al. January 10, 2	2006-01-10
Method of manufacture of silicon based package Grant 6,878,608 - Brofman , et al. April 12, 2	2005-04-12
Dielectric interposer for chip to substrate soldering Grant 6,657,313 - Brofman , et al. December 2, 2	2003-12-02
Dielectric interposer for chip to substrate soldering App 20030193093 - Brofman, Peter J. ; et al.	2003-10-16
Method for assembling a carrier and a semiconductor device Grant 6,584,684 - Brofman , et al. July 1, 2	2003-07-01
Method of manufacture of silicon based package and device manufactured thereby App 20020180013 - Brofman, Peter J. ; et al.	2002-12-05
Method of interconnecting electronic components using a plurality of conductive studs App 20010019178 - Brofman, Peter J. ; et al.	2001-09-06
Method for enhancing fatigue life of ball grid arrays Grant 6,283,359 - Brofman , et al. September 4, 2	2001-09-04
Process for forming cone shaped solder for chip interconnection App 20010015495 - Brofman, Peter J. ; et al.	2001-08-23
Solder disc connection Grant 6,278,184 - Brofman , et al. August 21, 2	2001-08-21
Z-axis compressible polymer with fine metal matrix suspension Grant 6,270,363 - Brofman , et al. August 7, 2	2001-08-07
Method for assembling a carrier and a semiconductor device App 20010007288 - Brofman, Peter J. ; et al.	2001-07-12
Method of interconnecting electronic components using a plurality of conductive studs Grant 6,258,625 - Brofman , et al. July 10, 2	2001-07-10
Method for enhancing fatigue life of ball grid arrays Grant 6,158,644 - Brofman , et al. December 12, 2	2000-12-12
Non-destructive low melt test for off-composition solder Grant 6,016,947 - Donahue , et al. January 25, 2	2000-01-25
Ceramic ball grid array using in-situ solder stretch Grant 5,975,409 - Brofman , et al. November 2, 1	1999-11-02
Enhanced ceramic ball grid array using in-situ solder stretch with spring Grant 5,968,670 - Brofman , et al. October 19, 1	1999-10-19
Enhanced ceramic ball grid array using in-situ solder stretch with clip Grant 5,964,396 - Brofman , et al. October 12, 1	1999-10-12
Electronic component package with decoupling capacitors completely within die receiving cavity of substrate Grant 5,831,810 - Bird , et al. November 3, 1	1998-11-03
Porous metal block for removing solder or braze from a substate and a process for making the same Grant 5,284,286 - Brofman , et al. February 8, 1	1994-02-08

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