Brockmann; Russell C

Patent Applications and Registrations

Patent applications and USPTO patent grants for Brockmann; Russell C.The latest application filed is for "method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine".

Company Profile

0.23.6

Brockmann; Russell C - Ft Collins CO
Brockmann; Russell C. - Fort Collins CO
Brockmann, Russell C. - Ft. Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine Grant 7,356,674 - Dua , et al. April 8, 2	2008-04-08
Method and apparatus for implementing two architectures in a chip Grant 7,343,479 - Knebel , et al. March 11, 2	2008-03-11
Method and apparatus for verifying the correctness of a processor behavioral model Grant 7,139,936 - Petsinger , et al. November 21, 2	2006-11-21
Method and apparatus to reduce penalty of microcode lookup Grant 6,789,186 - Brockmann , et al. September 7, 2	2004-09-07
Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine App 20040107335 - Dua, Anuj ; et al.	2004-06-03
Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition Grant 6,745,322 - Brockmann , et al. June 1, 2	2004-06-01
Method and apparatus for testing microarchitectural features by using tests written in microcode App 20040064267 - Safford, Kevin David ; et al.	2004-04-01
Method and apparatus for verifying the correctness of a processor behavioral model App 20040039966 - Petsinger, Jeremy ; et al.	2004-02-26
Apparatus and method for pseudorandom rare event injection to improve verification quality App 20040034820 - Soltis,, Donald C. JR. ; et al.	2004-02-19
Method and apparatus for implementing two architectures in a chip App 20040030865 - Knebel, Patrick ; et al.	2004-02-12
Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine Grant 6,678,817 - Dua , et al. January 13, 2	2004-01-13
Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM Grant 6,654,849 - Brockmann , et al. November 25, 2	2003-11-25
Method and apparatus for testing microarchitectural features by using tests written in microcode Grant 6,643,800 - Safford , et al. November 4, 2	2003-11-04
Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit Grant 6,625,759 - Petsinger , et al. September 23, 2	2003-09-23
Method and apparatus for reducing branch prediction table pollution Grant 6,622,241 - Brockmann , et al. September 16, 2	2003-09-16
Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information Grant 6,618,801 - Knebel , et al. September 9, 2	2003-09-09
Method And Apparatus For Reducing Branch Prediction Table Pollution App 20030163678 - Brockmann, Russell C. ; et al.	2003-08-28
Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns Grant 5,956,476 - Ranson , et al. September 21, 1	1999-09-21
Method for processing information in a microprocessor to facilitate debug and performance monitoring Grant 5,956,477 - Ranson , et al. September 21, 1	1999-09-21
Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results Grant 5,887,003 - Ranson , et al. March 23, 1	1999-03-23
System and method for on-chip debug support and performance monitoring in a microprocessor Grant 5,867,644 - Ranson , et al. February 2, 1	1999-02-02
Method for enhanced functional testing of a processor using dynamic trap handlers Grant 5,784,550 - Brockmann , et al. July 21, 1	1998-07-21
Speculative execution of test patterns in a random test generator Grant 5,729,554 - Weir , et al. March 17, 1	1998-03-17
Addressing method and apparatus for a computer system Grant 5,437,019 - Brockmann July 25, 1	1995-07-25
Flexible N-way memory interleaving Grant 5,293,607 - Brockmann , et al. March 8, 1	1994-03-08
Memory-resource-driven arbitration Grant 5,287,477 - Johnson , et al. February 15, 1	1994-02-15
Preservation of priority in computer bus arbitration Grant 5,265,223 - Brockmann , et al. November 23, 1	1993-11-23
Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle Grant 5,255,373 - Brockmann , et al. October 19, 1	1993-10-19
Methods and apparatus for carrying out transactions in a computer system Grant 5,249,297 - Brockmann , et al. September 28, 1	1993-09-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.