| Patent | Date |
|---|
Programmable interconnect for reconfigurable system-on-chip
Grant 7,650,545 - Abramovici , et al. January 19, 2 | 2010-01-19 |
Programmable termination for single-ended and differential schemes
Grant 7,262,630 - Andrews , et al. August 28, 2 | 2007-08-28 |
Protocol-independent packet delineation for backplane architecture
Grant 7,139,288 - Balay , et al. November 21, 2 | 2006-11-21 |
Adaptive input logic for phase adjustments
Grant 7,034,596 - Andrews , et al. April 25, 2 | 2006-04-25 |
Adaptive input logic for phase adjustments
App 20040155690 - Andrews, William B. ; et al. | 2004-08-12 |
Protocol-independent packet delineation for backplane architecture
App 20040071224 - Balay, Francois ; et al. | 2004-04-15 |
Multi-master multi-slave system bus in a field programmable gate array (FPGA)
Grant 6,483,342 - Britton , et al. November 19, 2 | 2002-11-19 |
Double data rate input and output in a programmable logic device
Grant 6,472,904 - Andrews , et al. October 29, 2 | 2002-10-29 |
Multi-master multi-slave system bus in a field programmable gate array (FPGA)
App 20020008540 - Britton, Barry K. ; et al. | 2002-01-24 |
Double data rate input and output in a programmable logic device
App 20020003436 - Andrews, William B. ; et al. | 2002-01-10 |
Field programmable gate array having a dedicated processor interface
Grant 6,216,191 - Britton , et al. April 10, 2 | 2001-04-10 |
Global signal distribution with reduced routing tracks in an FPGA
Grant 6,064,225 - Andrews , et al. May 16, 2 | 2000-05-16 |
Programmable clock manager for a programmable logic device that can implement delay-locked loop functions
Grant 6,043,677 - Albu , et al. March 28, 2 | 2000-03-28 |
Programmable clock manager for a programmable logic device that can generate at least two different output clocks
Grant 6,028,463 - Albu , et al. February 22, 2 | 2000-02-22 |
Hybrid programmable gate arrays
Grant 6,020,755 - Andrews , et al. February 1, 2 | 2000-02-01 |
Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices
Grant 5,986,471 - Britton , et al. November 16, 1 | 1999-11-16 |
Field programmable gate array with write-port enabled memory
Grant 5,623,217 - Britton , et al. April 22, 1 | 1997-04-22 |
Low-skew signal routing in a programmable array
Grant 5,528,170 - Britton , et al. June 18, 1 | 1996-06-18 |
FPGA with distributed switch matrix
Grant 5,396,126 - Britton , et al. March 7, 1 | 1995-03-07 |
Apparatus and method to improve programming speed of field programmable gate arrays
Grant 5,394,031 - Britton , et al. February 28, 1 | 1995-02-28 |
Programmable function unit with programmable fast ripple logic
Grant 5,386,156 - Britton , et al. January 31, 1 | 1995-01-31 |
Low-skew signal routing in a programmable array
Grant 5,384,497 - Britton , et al. January 24, 1 | 1995-01-24 |
FPGA having PFU with programmable output driver inputs
Grant 5,381,058 - Britton , et al. January 10, 1 | 1995-01-10 |
Field programmable gate array with direct input/output connection
Grant 5,311,080 - Britton , et al. May 10, 1 | 1994-05-10 |
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