Britton; Barry

Patent Applications and Registrations

Patent applications and USPTO patent grants for Britton; Barry.The latest application filed is for "phase locked loop circuit with selectable feedback paths".

Company Profile

1.18.5

Britton; Barry - Slatington PA
Britton; Barry - Hillsboro OR
Britton; Barry - Allentown PA
Britton; Barry - Orefield PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Single event upset immune flip-flop utilizing a small-area highly resistive element Grant 10,819,318 - Britton , et al. October 27, 2	2020-10-27
Phase Locked Loop Circuit With Selectable Feedback Paths App 20140009194 - Britton; Barry ; et al.	2014-01-09
Phase locked loop circuit with selectable feedback paths Grant 8,531,222 - Britton , et al. September 10, 2	2013-09-10
Safe programming of key information into non-volatile memory for a programmable logic device Grant 8,319,521 - Han , et al. November 27, 2	2012-11-27
Power control block with output glitch protection Grant 8,314,634 - Britton , et al. November 20, 2	2012-11-20
Flexible delay cell architecture Grant 7,863,931 - Zhang , et al. January 4, 2	2011-01-04
Programmable logic device with multiple slice types Grant 7,696,784 - Agrawal , et al. April 13, 2	2010-04-13
Dual-slice architectures for programmable logic devices Grant 7,675,321 - Agrawal , et al. March 9, 2	2010-03-09
Area efficient routing architectures for programmable logic devices Grant 7,605,606 - Ding , et al. October 20, 2	2009-10-20
Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits Grant 7,599,457 - Johnson , et al. October 6, 2	2009-10-06
Logic block control architectures for programmable logic devices Grant 7,592,834 - Agrawal , et al. September 22, 2	2009-09-22
Efficient configuration of daisy-chained programmable logic devices Grant 7,554,357 - Chen , et al. June 30, 2	2009-06-30
Distributed multiple-channel alignment scheme Grant 7,532,646 - Leung , et al. May 12, 2	2009-05-12
Logic block control architectures for programmable logic devices Grant 7,397,276 - Agrawal , et al. July 8, 2	2008-07-08
Dual slice architectures for programmable logic devices Grant 7,385,417 - Agrawal , et al. June 10, 2	2008-06-10
Programmable logic device architecture with multiple slice types Grant 7,378,872 - Agrawal , et al. May 27, 2	2008-05-27
Efficient configuration of daisy-chained programmable logic devices App 20070182445 - Chen; Zheng (Jeff) ; et al.	2007-08-09
Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits App 20070030936 - Johnson; Phillip ; et al.	2007-02-08
Distributed multiple-channel alignment scheme App 20060187966 - Leung; Wai-Bor ; et al.	2006-08-24
Programmable broadcast initialization of memory blocks Grant 6,940,779 - Chen , et al. September 6, 2	2005-09-06
Method and apparatus for controlling signal distribution in an electronic circuit Grant 6,873,187 - Andrews , et al. March 29, 2	2005-03-29
Programmable broadcast initialization of memory blocks App 20050035781 - Chen, Zheng (Jeff) ; et al.	2005-02-17

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