| Patent | Date |
|---|
Low-H plasma treatment with N.sub.2 anneal for electronic memory devices
Grant 8,202,810 - Nickel , et al. June 19, 2 | 2012-06-19 |
Low-h Plasma Treatment With N2 Anneal For Electronic Memory Devices
App 20090176369 - Nickel; Alexander H. ; et al. | 2009-07-09 |
Method And Apparatus For Detecting The Endpoint Of A Chemical-Mechanical Polishing Operation
App 20070105247 - Mauersberger; Frank ; et al. | 2007-05-10 |
Closed loop residual gas analyzer process control technique
Grant 6,955,928 - Brennan October 18, 2 | 2005-10-18 |
Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques
Grant 6,809,032 - Mauersberger , et al. October 26, 2 | 2004-10-26 |
Method and apparatus for controlling copper barrier/seed deposition processes
Grant 6,800,494 - Castle , et al. October 5, 2 | 2004-10-05 |
Transistor having a gate stick comprised of a metal, and a method of making same
Grant 6,614,064 - Besser , et al. September 2, 2 | 2003-09-02 |
Method for forming openings for conductive interconnects
Grant 6,555,479 - Hause , et al. April 29, 2 | 2003-04-29 |
Test structure for providing depth of polish feedback
Grant 6,514,858 - Hause , et al. February 4, 2 | 2003-02-04 |
Method for forming copper interconnects
Grant 6,489,240 - Iacoponi , et al. December 3, 2 | 2002-12-03 |
Contact each methodology and integration scheme
Grant 6,413,846 - Besser , et al. July 2, 2 | 2002-07-02 |
Dielectric having an air gap formed between closely spaced interconnect lines
Grant 6,376,330 - Fulford, Jr. , et al. April 23, 2 | 2002-04-23 |
Semiconductor Isolation Region Bounded By A Trench And Covered With An Oxide To Improve Planarization
App 20010020727 - HAUSE, FRED N. ; et al. | 2001-09-13 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 6,208,015 - Bandyopadhyay , et al. March 27, 2 | 2001-03-27 |
Thin titanium film as self-regulating filter for silicon migration into aluminum metal lines
Grant 6,191,032 - Tiffin , et al. February 20, 2 | 2001-02-20 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer
Grant 6,153,833 - Dawson , et al. November 28, 2 | 2000-11-28 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 6,150,721 - Bandyopadhyay , et al. November 21, 2 | 2000-11-21 |
Integrated circuit having conductors of enhanced cross-sectional area
Grant 6,127,264 - Bandyopadhyay , et al. October 3, 2 | 2000-10-03 |
Dissolvable dielectric method and structure
Grant 6,091,149 - Hause , et al. July 18, 2 | 2000-07-18 |
Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect
Grant 6,060,389 - Brennan , et al. May 9, 2 | 2000-05-09 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
Grant 6,031,289 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,998,293 - Dawson , et al. December 7, 1 | 1999-12-07 |
Method of planarizing a semiconductor topography using multiple polish pads
Grant 5,968,843 - Dawson , et al. October 19, 1 | 1999-10-19 |
Dissolvable dielectric method
Grant 5,953,626 - Hause , et al. September 14, 1 | 1999-09-14 |
Method for achieving global planarization by forming minimum mesas in large field areas
Grant 5,926,713 - Hause , et al. July 20, 1 | 1999-07-20 |
Method of making an integrated circuit with oxidizable trench liner
Grant 5,926,717 - Michael , et al. July 20, 1 | 1999-07-20 |
Integrated circuit having horizontally and vertically offset interconnect lines
Grant 5,854,131 - Dawson , et al. December 29, 1 | 1998-12-29 |
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
Grant 5,851,913 - Brennan , et al. December 22, 1 | 1998-12-22 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
Grant 5,850,105 - Dawson , et al. December 15, 1 | 1998-12-15 |
Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
Grant 5,847,462 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 5,846,876 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
Grant 5,827,776 - Bandyopadhyay , et al. October 27, 1 | 1998-10-27 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 5,814,555 - Bandyopadhyay , et al. September 29, 1 | 1998-09-29 |
Interlevel dielectric with air gaps to reduce permitivity
Grant 5,792,706 - Michael , et al. August 11, 1 | 1998-08-11 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,783,864 - Dawson , et al. July 21, 1 | 1998-07-21 |
Semiconductor interlevel dielectric having a polymide for producing air gaps
Grant 5,783,481 - Brennan , et al. July 21, 1 | 1998-07-21 |
Method of forming a recessed interconnect structure
Grant 5,767,012 - Fulford, Jr. , et al. June 16, 1 | 1998-06-16 |
Method of formation of an air gap within a semiconductor dielectric by solvent desorption
Grant 5,759,913 - Fulford, Jr. , et al. June 2, 1 | 1998-06-02 |
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