Braun; Georg

Patent Applications and Registrations

Patent applications and USPTO patent grants for Braun; Georg.The latest application filed is for "distributed command and address bus architecture".

Company Profile

0.37.59

Braun; Georg - Holzkirchen DE
Braun; Georg - Munich DE
Braun; Georg - Munchen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed Grant 8,161,219 - Bruennert , et al. April 17, 2	2012-04-17
Bus termination system and method Grant 8,041,865 - Bruennert , et al. October 18, 2	2011-10-18
Apparatus and method for providing a signal for transmission via a signal line Grant 7,936,201 - Prete , et al. May 3, 2	2011-05-03
High speed memory architecture Grant 7,848,153 - Bruennert , et al. December 7, 2	2010-12-07
Command protocol for integrated circuits Grant 7,844,798 - Gartner , et al. November 30, 2	2010-11-30
Memory dies for flexible use and method for configuring memory dies Grant 7,796,446 - Ruckerbauer , et al. September 14, 2	2010-09-14
Horizontal dual in-line memory modules Grant 7,771,206 - Bruennert , et al. August 10, 2	2010-08-10
Apparatus and method for switching an apparatus to a power saving mode Grant 7,721,130 - Prete , et al. May 18, 2	2010-05-18
Distributed Command and Address Bus Architecture App 20100082871 - Bruennert; Michael ; et al.	2010-04-01
Memory Dies for Flexible Use and Method for Configuring Memory Dies App 20100074038 - Ruckerbauer; Hermann ; et al.	2010-03-25
Horizontal Dual In-line Memory Modules App 20100062621 - BRUENNERT; MICHAEL ; et al.	2010-03-11
High Speed Memory Architecture App 20100046266 - Bruennert; Michael ; et al.	2010-02-25
Stacked Memory Module App 20100032820 - Bruennert; Michael ; et al.	2010-02-11
Bus Termination System and Method App 20100030934 - Bruennert; Michael ; et al.	2010-02-04
Buffer component for a memory module, and a memory module and a memory system having such buffer component Grant 7,646,650 - Braun , et al. January 12, 2	2010-01-12
Command Protocol for Integrated Circuits App 20090158010 - Gartner; Andreas ; et al.	2009-06-18
Memory chip with settable termination resistance circuit Grant 7,532,523 - Braun , et al. May 12, 2	2009-05-12
Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted Grant 7,457,174 - Braun , et al. November 25, 2	2008-11-25
Buffer chip and method for controlling one or more memory arrangements Grant 7,447,805 - Braun , et al. November 4, 2	2008-11-04
Integrated semiconductor memory with determination of a chip temperature Grant 7,440,349 - Braun , et al. October 21, 2	2008-10-21
Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage Grant 7,405,591 - Braun , et al. July 29, 2	2008-07-29
Semiconductor memory array with serial control/address bus Grant 7,397,684 - Ruckerbauer , et al. July 8, 2	2008-07-08
Apparatus and method for providing a signal for transmission via a signal line App 20080155150 - Prete; Edoardo ; et al.	2008-06-26
Concept For Interfacing A First Circuit Requiring A First Supply Voltage And A Second Supply Circuit Requiring A Second Supply Voltage App 20080143386 - Braun; Georg ; et al.	2008-06-19
Apparatus and method for switching an apparatus to a power saving mode App 20080126816 - Prete; Edoardo ; et al.	2008-05-29
Apparatus and method for transmitting signals over a signal line App 20080123792 - Prete; Edoardo ; et al.	2008-05-29
Memory buffer and method for buffering data App 20080126624 - Prete; Edoardo ; et al.	2008-05-29
Memory arrangement Grant 7,376,802 - Braun , et al. May 20, 2	2008-05-20
System for determining a reference level and evaluating a signal on the basis of the reference level Grant 7,362,622 - Braun , et al. April 22, 2	2008-04-22
DQS signaling in DDR-III memory systems without preamble Grant 7,342,815 - Ruckerbauer , et al. March 11, 2	2008-03-11
Memory With A Temperature Sensor, Dynamic Memory And Memory With A Clock Unit And Method Of Sensing A Temperature Of A Memory App 20070223299 - Egerer; Jens Christoph ; et al.	2007-09-27
Memory module and method for operating a memory module in a data memory system Grant 7,275,189 - Ruckerbauer , et al. September 25, 2	2007-09-25
Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory Grant 7,272,063 - Egerer , et al. September 18, 2	2007-09-18
Integrated semiconductor memory with determination of a chip temperature App 20070133329 - Braun; Georg ; et al.	2007-06-14
Semiconductor memory array with serial control/address bus App 20070058408 - Ruckerbauer; Hermann ; et al.	2007-03-15
Memory Chip And Method For Operating A Memory Chip App 20070035326 - Braun; Georg ; et al.	2007-02-15
Method and circuit for allocating memory arrangement addresses Grant 7,149,864 - Braun , et al. December 12, 2	2006-12-12
Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted App 20060262613 - Braun; Georg ; et al.	2006-11-23
Transmitting data into a memory cell array Grant 7,139,290 - Braun November 21, 2	2006-11-21
Method for determining the optimum access strategy Grant 7,127,553 - Benedix , et al. October 24, 2	2006-10-24
Buffer component for a memory module, and a memory module and a memory system having such buffer component App 20060227627 - Braun; Georg ; et al.	2006-10-12
Memory module and memory configuration with stub-free signal lines and distributed capacitive loads App 20060202328 - Braun; Georg ; et al.	2006-09-14
Circuit App 20060092715 - Braun; Georg ; et al.	2006-05-04
DQS signaling in DDR-III memory systems without preamble App 20060062039 - Ruckerbauer; Hermann ; et al.	2006-03-23
Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit Grant 6,958,613 - Braun , et al. October 25, 2	2005-10-25
Integrated circuit Grant 6,911,732 - Muff , et al. June 28, 2	2005-06-28
Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor Grant 6,894,330 - Bachhofer , et al. May 17, 2	2005-05-17
Memory arrangement App 20050038966 - Braun, Georg ; et al.	2005-02-17
Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops Grant 6,833,731 - Lauterbach , et al. December 21, 2	2004-12-21
Buffer chip and method for actuating one or more memory arrangements App 20040228166 - Braun, Georg ; et al.	2004-11-18
Synchronous memory system and also method and protocol for communication in a synchronous memory system App 20040230759 - Braun, Georg ; et al.	2004-11-18
Data processing system having configurable components Grant 6,820,197 - Benedix , et al. November 16, 2	2004-11-16
Method and circuit for allocating memory arrangement addresses App 20040225856 - Braun, Georg ; et al.	2004-11-11
Memory module and method for operating a memory module in a data memory system App 20040151038 - Ruckerbauer, Hermann ; et al.	2004-08-05
Integrated circuit App 20040145036 - Muff, Simon ; et al.	2004-07-29
Electronic circuit with a driver circuit Grant 6,759,874 - Braun , et al. July 6, 2	2004-07-06
Method for determining the optimum access strategy App 20040117800 - Benedix, Alexander ; et al.	2004-06-17
Memory module and memory configuration with stub-free signal lines and distributed capacitive loads App 20040085795 - Braun, Georg ; et al.	2004-05-06
Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit App 20040080322 - Braun, Georg ; et al.	2004-04-29
Configuration for data transmission in a semiconductor memory system, and relevant data transmission method Grant 6,724,685 - Braun , et al. April 20, 2	2004-04-20
Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement Grant 6,715,138 - Braun March 30, 2	2004-03-30
Ferroelectric read/write memory with series-connected memory cells (CFRAM) Grant 6,697,279 - Schneider , et al. February 24, 2	2004-02-24
Monolithically integrable inductor Grant 6,635,947 - Benedix , et al. October 21, 2	2003-10-21
Memory device Grant 6,624,461 - Hoenigschmid , et al. September 23, 2	2003-09-23
Configuration for data transmission in a semiconductor memory system, and relevant data transmission method App 20030099149 - Braun, Georg ; et al.	2003-05-29
Data processing system having configurable components App 20030093587 - Benedix, Alexander ; et al.	2003-05-15
Electronic circuit with a driver circuit App 20030057994 - Braun, Georg ; et al.	2003-03-27
Transmitting data into a memory cell array App 20030012229 - Braun, Georg	2003-01-16
Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement App 20030014723 - Braun, Georg	2003-01-16
Integrated memory having memory cells and reference cells, and operating method for such a memory Grant 6,487,128 - Bohm , et al. November 26, 2	2002-11-26
Method for fabricating a ferroelectric memory configuration App 20020110935 - Bergmann, Renate ; et al.	2002-08-15
Charge pump App 20020075065 - Esterl, Robert ; et al.	2002-06-20
Integrated memory having memory cells and reference cells, and corresponding operating method App 20020071317 - Bohm, Thomas ; et al.	2002-06-13
Method and device for processing data in a memory unit App 20020062431 - Benedix, Alexander ; et al.	2002-05-23
Operating method for an integrated memory having writeable memory cells and corresponding integrated memory App 20020046385 - Boehm, Thomas ; et al.	2002-04-18
Integrated memory and corresponding operating method App 20020044493 - Bohm, Thomas ; et al.	2002-04-18
Monolithically integrable inductor App 20020041004 - Benedix, Alexander ; et al.	2002-04-11
Integrated memory having memory cells and reference cells, and operating method for such a memory App 20020027816 - Bohm, Thomas ; et al.	2002-03-07
Circuit configuration for reading a memory cell having a ferroelectric capacitor App 20020024836 - Braun, Georg ; et al.	2002-02-28
Integrated memory having a differential sense amplifier Grant 6,351,422 - Rohr , et al. February 26, 2	2002-02-26
Integrated memory with redundancy App 20020015337 - Neuhold, Ernst ; et al.	2002-02-07
Decoder element for generating an output signal having three different potentials and an operating method for the decoder element App 20020008564 - Bohm, Thomas ; et al.	2002-01-24
Integrated memory App 20020003735 - Bohm, Thomas ; et al.	2002-01-10
Integrated memory with redundancy and method for repairing an integrated memory App 20020003728 - Honigschmid, Heinz ; et al.	2002-01-10
Ferroelectric transistor and method for fabricating it App 20010042888 - Willer, Josef ; et al.	2001-11-22
Integrated memory having a differential sense amplifier App 20010038562 - Rohr, Thomas ; et al.	2001-11-08
Circuit configuration for generating a reference voltage for reading a ferroelectric memory App 20010038557 - Braun, Georg ; et al.	2001-11-08
Integrated memory with plate line segments App 20010030894 - Braun, Georg ; et al.	2001-10-18
Semiconductor circuit configuration App 20010028090 - Braun, Georg ; et al.	2001-10-11
Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration App 20010026491 - Bohm, Thomas ; et al.	2001-10-04
Decoder element for producing an output signal having three different potentials App 20010026485 - Rohr, Thomas ; et al.	2001-10-04
Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor App 20010017386 - Bachhofer, Harald ; et al.	2001-08-30
Ferroelectric read/write memory with series-connected memory cells (CFRAM) App 20010015906 - Schneider, Ronny ; et al.	2001-08-23
Ferroelectric memory array App 20010012213 - Braun, Georg ; et al.	2001-08-09
Method for writing and reading a ferroelectric memory App 20010005326 - Braun, Georg	2001-06-28
Ferroelectric memory and method for preventing aging in a memory cell Grant 6,091,625 - Braun , et al. July 18, 2	2000-07-18

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