| Patent | Date |
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Interference reduction circuit for touch system
Grant 10,423,277 - Hosur , et al. Sept | 2019-09-24 |
Interference Reduction Circuit For Touch System
App 20180188888 - HOSUR; SRINATH ; et al. | 2018-07-05 |
Closed-loop high-speed channel equalizer adaptation
Grant 9,602,318 - Sperlich , et al. March 21, 2 | 2017-03-21 |
Logical to Multi-Variable-Record Connect Element to Interface Logical Signals Between Analog and Digital Simulations
App 20170024504 - Branch; Charles M. | 2017-01-26 |
Closed-loop High-speed Channel Equalizer Adaptation
App 20150341194 - Sperlich; Roland ; et al. | 2015-11-26 |
ESD robust level shifter
Grant 9,154,133 - Ali , et al. October 6, 2 | 2015-10-06 |
Closed-loop high-speed channel equalizer adaptation
Grant 9,130,792 - Sperlich , et al. September 8, 2 | 2015-09-08 |
Closed-loop High-speed Channel Equalizer Adaptation
App 20140362900 - Sperlich; Roland ; et al. | 2014-12-11 |
Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
Grant 8,692,592 - Branch , et al. April 8, 2 | 2014-04-08 |
ESD Robust Level Shifter
App 20130077196 - ALI; Muhammad Yusuf ; et al. | 2013-03-28 |
Efficient Retimer For Clock Dividers
App 20110193598 - Bhakta; Bhavesh G. ; et al. | 2011-08-11 |
Scan testable register file
Grant 7,908,535 - Branch , et al. March 15, 2 | 2011-03-15 |
Scan Testable Register File
App 20100332929 - Branch; Charles M. ; et al. | 2010-12-30 |
Digital design component with scan clock generation
Grant 7,650,549 - Branch , et al. January 19, 2 | 2010-01-19 |
Method and system for correcting signal integrity crosstalk violations
Grant 7,644,383 - Bartling , et al. January 5, 2 | 2010-01-05 |
Systems and devices for implementing sub-threshold memory devices
Grant 7,626,850 - Branch , et al. December 1, 2 | 2009-12-01 |
Digital storage element architecture comprising dual scan clocks and gated scan output
Grant 7,596,732 - Branch , et al. September 29, 2 | 2009-09-29 |
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content
Grant 7,587,577 - Royer , et al. September 8, 2 | 2009-09-08 |
Digital storage element with enable signal gating
Grant 7,487,417 - Branch , et al. February 3, 2 | 2009-02-03 |
Systems and Devices for Sub-threshold Data Capture
App 20080258790 - Branch; Charles M. ; et al. | 2008-10-23 |
Systems and Devices for Implementing Sub-Threshold Memory Devices
App 20080259681 - Branch; Charles M. ; et al. | 2008-10-23 |
Apparatus and method for generating pulses
Grant 7,425,859 - Branch , et al. September 16, 2 | 2008-09-16 |
Digital storage element architecture comprising dual scan clocks and preset functionality
Grant 7,375,567 - Branch , et al. May 20, 2 | 2008-05-20 |
Digital storage element with dual behavior
Grant 7,345,518 - Branch , et al. March 18, 2 | 2008-03-18 |
Digital storage element architecture comprising dual scan clocks and reset functionality
Grant 7,315,191 - Branch , et al. January 1, 2 | 2008-01-01 |
Apparatus And Method For Generating Pulses
App 20070229135 - Branch; Charles M. ; et al. | 2007-10-04 |
Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
Grant 7,274,233 - Branch , et al. September 25, 2 | 2007-09-25 |
Digital storage element architecture comprising integrated multiplexer and reset functionality
Grant 7,274,234 - Branch , et al. September 25, 2 | 2007-09-25 |
Apparatus and method for generating pulses
Grant 7,236,036 - Branch , et al. June 26, 2 | 2007-06-26 |
Low-Power Co-Processor Architecture
App 20070113048 - Royer; Marc E. ; et al. | 2007-05-17 |
Digital storage element architecture comprising dual scan clocks and gated scan output
App 20070022344 - Branch; Charles M. ; et al. | 2007-01-25 |
Digital storage element with enable signal gating
App 20070022336 - Branch; Charles M. ; et al. | 2007-01-25 |
Digital design component with scan clock generation
App 20070022339 - Branch; Charles M. ; et al. | 2007-01-25 |
Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
App 20070001733 - Branch; Charles M. ; et al. | 2007-01-04 |
Digital storage element architecture comprising dual scan clocks and reset functionality
App 20070001728 - Branch; Charles M. ; et al. | 2007-01-04 |
Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
App 20070001730 - Branch; Charles M. ; et al. | 2007-01-04 |
Digital storage element with dual behavior
App 20070001732 - Branch; Charles M. ; et al. | 2007-01-04 |
Digital storage element architecture comprising dual scan clocks and preset functionality
App 20070001729 - Branch; Charles M. ; et al. | 2007-01-04 |
Digital storage element architecture comprising integrated multiplexer and reset functionality
App 20070001731 - Branch; Charles M. ; et al. | 2007-01-04 |
Method and system for correcting signal integrity crosstalk violations
App 20070006109 - Bartling; Steven C. ; et al. | 2007-01-04 |
Method and system for synthesis of flip-flops
App 20070006105 - Bartling; Steven C. ; et al. | 2007-01-04 |
Method and system for desensitization of chip designs from perturbations affecting timing and manufacturability
App 20070006106 - Bartling; Steven C. ; et al. | 2007-01-04 |
Apparatus and method for generating pulses
App 20060226885 - Branch; Charles M. ; et al. | 2006-10-12 |
Delay circuit with current steering output symmetry and supply voltage insensitivity
Grant 6,690,242 - Fang , et al. February 10, 2 | 2004-02-10 |
Low jitter ring oscillator architecture
Grant 6,650,191 - Branch , et al. November 18, 2 | 2003-11-18 |
Delay circuit with current steering output symmetry and supply voltage insensitivity
App 20030117202 - Fang, Lieyi ; et al. | 2003-06-26 |
Low Jitter ring oscillator architecture
App 20030076179 - Branch, Charles M. ; et al. | 2003-04-24 |
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