Brain; Ruth

Patent Applications and Registrations

Patent applications and USPTO patent grants for Brain; Ruth.The latest application filed is for "etch-stop layer topography for advanced integrated circuit structure fabrication".

Company Profile

8.7.10

Brain; Ruth - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology Grant 11,322,504 - Avci , et al. May 3, 2	2022-05-03
Etch-stop layer topography for advanced integrated circuit structure fabrication Grant 10,943,817 - Yeoh , et al. March 9, 2	2021-03-09
Etch-stop layer topography for advanced integrated circuit structure fabrication Grant 10,796,951 - Yeoh , et al. October 6, 2	2020-10-06
Etch-stop Layer Topography For Advanced Integrated Circuit Structure Fabrication App 20200027781 - YEOH; Andrew W. ; et al.	2020-01-23
Ferroelectric-capacitor Integration Using Novel Multi-metal-level Interconnect With Replaced Dielectric For Ultra-dense Embedded App 20200006352 - AVCI; Uygar ; et al.	2020-01-02
Replacement Metal Cob Integration Process For Embedded Dram App 20200006346 - AVCI; Uygar ; et al.	2020-01-02
Etch-stop Layer Topography For Advanced Integrated Circuit Structure Fabrication App 20190164818 - YEOH; Andrew W. ; et al.	2019-05-30
Fabrication of interconnects in a low-k interlayer dielectrics Grant 8,143,159 - King , et al. March 27, 2	2012-03-27
Winged vias to increase overlay margin Grant 8,058,177 - Weiss , et al. November 15, 2	2011-11-15
Fabrication of interconnects in a low-k interlayer dielectrics App 20110003471 - King; Sean ; et al.	2011-01-06
Interconnect in low-k interlayer dielectrics Grant 7,812,455 - King , et al. October 12, 2	2010-10-12
Winged Vias To Increase Overlay Margin App 20100025858 - Weiss; Martin ; et al.	2010-02-04
Fabrication Of Interconnects In Low-k Interlayer Dielectrics App 20090309227 - King; Sean ; et al.	2009-12-17
Method integrating polymeric interlayer dielectric in integrated circuits Grant 6,774,037 - Hussein , et al. August 10, 2	2004-08-10
Method integrating polymeric interlayer dielectric in integrated circuits App 20030216057 - Hussein, Makarem A. ; et al.	2003-11-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.