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Photonics-Optimized Processor System
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Photonics-Optimized Processor System
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Photonics-Optimized Processor System
App 20160314070 - Dutt; Birendra ; et al. | 2016-10-27 |
Photonics-Optimized Processor System
App 20160314091 - Dutt; Birendra ; et al. | 2016-10-27 |
Photonics-Optimized Processor System
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Dynamic Random Access Memory Having Junction Field Effect Transistor Cell Access Device
App 20120009743 - Boyle; Douglas B. | 2012-01-12 |
Dynamic random access memory having junction field effect transistor cell access device
Grant 8,035,139 - Boyle October 11, 2 | 2011-10-11 |
Dynamic Random Access Memory Having Junction Field Effect Transistor Cell Access Device
App 20090057728 - Boyle; Douglas B. | 2009-03-05 |
Placement method for integrated circuit design using topo-clustering
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Method and apparatus for mapping platform-based design to multiple foundry processes
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Method for design optimization using logical and physical information
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Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
Grant 6,493,658 - Koford , et al. December 10, 2 | 2002-12-10 |
Placement method for integrated circuit design using topo-clustering
App 20020138816 - Sarrafzadeh, Majid ; et al. | 2002-09-26 |
Placement method for integrated circuit design using topo-clustering
Grant 6,442,743 - Sarrafzadeh , et al. August 27, 2 | 2002-08-27 |
System and method for concurrent placement of gates and associated wiring
Grant 6,385,760 - Pileggi , et al. May 7, 2 | 2002-05-07 |
System and method for concurrent buffer insertion and placement of logic gates
Grant 6,367,051 - Pileggi , et al. April 2, 2 | 2002-04-02 |
System And Method For Concurrent Placement Of Gates And Associated Wiring
App 20010047507 - PILEGGI, LAWRENCE ; et al. | 2001-11-29 |
Method for design optimization using logical and physical information
Grant 6,286,128 - Pileggi , et al. September 4, 2 | 2001-09-04 |
Method for design optimization using logical and physical information
App 20010010090 - Boyle, Douglas B. ; et al. | 2001-07-26 |
Method for logic optimization for improving timing and congestion during placement in integrated circuit design
Grant 6,192,508 - Malik , et al. February 20, 2 | 2001-02-20 |
Cell placement representation and transposition for integrated circuit physical design automation system
Grant 6,155,725 - Scepanovic , et al. December 5, 2 | 2000-12-05 |
Microprocessor having instruction set extensions for decryption and multimedia applications
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Method for providing performance-driven logic optimization in an integrated circuit layout design
Grant 6,099,580 - Boyle , et al. August 8, 2 | 2000-08-08 |
Single chip systems using general purpose processors
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Congestion based cost factor computing apparatus for integrated circuit physical design automation system
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Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows
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Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
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Optimization processing for integrated circuit physical design automation system using parallel moving windows
Grant 5,870,313 - Boyle , et al. February 9, 1 | 1999-02-09 |
System and method for maintaining a shared cache look-up table
Grant 5,864,854 - Boyle January 26, 1 | 1999-01-26 |
Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
Grant 5,815,403 - Jones , et al. September 29, 1 | 1998-09-29 |
Cell placement alteration apparatus for integrated circuit chip physical design automation system
Grant 5,793,644 - Koford , et al. August 11, 1 | 1998-08-11 |
Method for producing integrated circuit chip having optimized cell placement
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Single chip multiprocessor architecture with internal task switching synchronization bus
Grant 5,761,516 - Rostoker , et al. June 2, 1 | 1998-06-02 |
Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations
Grant 5,745,363 - Rostoker , et al. April 28, 1 | 1998-04-28 |
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
Grant 5,742,510 - Rostoker , et al. April 21, 1 | 1998-04-21 |
Computer implemented method for producing optimized cell placement for integrated circiut chip
Grant 5,636,125 - Rostoker , et al. June 3, 1 | 1997-06-03 |
Method of cell placement for an itegrated circuit chip comprising integrated placement and cell overlap removal
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Cell placement alteration apparatus for integrated circuit chip physical design automation system
Grant 5,557,533 - Koford , et al. September 17, 1 | 1996-09-17 |
Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
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