Boyd; Diane C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Boyd; Diane C..The latest application filed is for "cmos silicide metal gate integration".

Company Profile

0.31.29

Boyd; Diane C. - LaGrangeville NY US
Boyd; Diane C - LaGrangeville NY
Boyd, Diane C. - Langrangeville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and structure for strained FinFET devices Grant 8,669,145 - Doris , et al. March 11, 2	2014-03-11
Oxidation method for altering a film structure Grant 7,741,166 - Belyansky , et al. June 22, 2	2010-06-22
CMOS silicide metal gate integration Grant 7,655,557 - Amos , et al. February 2, 2	2010-02-02
Method and structure for strained FinFET devices Grant 7,602,021 - Doris , et al. October 13, 2	2009-10-13
Stressed semiconductor device structures having granular semiconductor material Grant 7,488,658 - Doris , et al. February 10, 2	2009-02-10
Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique Grant 7,482,243 - Boyd , et al. January 27, 2	2009-01-27
Cmos Silicide Metal Gate Integration App 20080254622 - Amos; Ricky S. ; et al.	2008-10-16
HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS App 20080251813 - Boyd; Diane C. ; et al.	2008-10-16
CMOS silicide metal gate integration Grant 7,411,227 - Amos , et al. August 12, 2	2008-08-12
Hetero-integrated strained silicon n- and p-MOSFETs Grant 7,396,747 - Boyd , et al. July 8, 2	2008-07-08
Stressed Semiconductor Device Structures Having Granular Semiconductor Material App 20080064172 - Doris; Bruce B. ; et al.	2008-03-13
HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS App 20070278517 - Boyd; Diane C. ; et al.	2007-12-06
ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE App 20070228473 - Boyd; Diane C. ; et al.	2007-10-04
Hetero-integrated strained silicon n- and p-MOSFETs Grant 7,273,800 - Boyd , et al. September 25, 2	2007-09-25
Hybrid planar and FinFET CMOS devices Grant 7,250,658 - Doris , et al. July 31, 2	2007-07-31
Ultra-thin Si MOSFET device structure and method of manufacture Grant 7,247,569 - Boyd , et al. July 24, 2	2007-07-24
Method and structure for strained FinFET devices App 20070132039 - Doris; Bruce Bennett ; et al.	2007-06-14
CMOS transistor structure including film having reduced stress by exposure to atomic oxygen Grant 7,202,516 - Belyansky , et al. April 10, 2	2007-04-10
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 7,166,521 - Boyd , et al. January 23, 2	2007-01-23
Ultrathin-body schottky contact MOSFET App 20070001223 - Boyd; Diane C. ; et al.	2007-01-04
Stressed semiconductor device structures having granular semiconductor material Grant 7,122,849 - Doris , et al. October 17, 2	2006-10-17
Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique App 20060211184 - Boyd; Diane C. ; et al.	2006-09-21
CMOS silicide metal gate integration App 20060189061 - Amos; Ricky S. ; et al.	2006-08-24
Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique Grant 7,075,150 - Boyd , et al. July 11, 2	2006-07-11
CMOS transistor structure including film having reduced stress by exposure to atomic oxygen App 20060131659 - Belyansky; Michael P. ; et al.	2006-06-22
CMOS silicide metal gate integration Grant 7,056,782 - Amos , et al. June 6, 2	2006-06-06
Oxidation method for altering a film structure App 20060105516 - Belyansky; Michael P. ; et al.	2006-05-18
Hetero-integrated strained silicon n-and p-MOSFETs App 20060091377 - Boyd; Diane C. ; et al.	2006-05-04
Ultra-thin body super-steep retrograde well (SSRW) FET devices Grant 7,002,214 - Boyd , et al. February 21, 2	2006-02-21
Ultra-thin Body Super-steep Retrograde Well (ssrw) Fet Devices App 20060022270 - Boyd; Diane C. ; et al.	2006-02-02
Method And Structure For Strained Finfet Devices App 20060014338 - Doris; Bruce Bennett ; et al.	2006-01-19
Oxidation method for altering a film structure and CMOS transistor structure formed therewith Grant 6,982,196 - Belyansky , et al. January 3, 2	2006-01-03
Hybrid planar and FinFET CMOS devices App 20050263831 - Doris, Bruce B. ; et al.	2005-12-01
CMOS silicide metal gate integration App 20050186747 - Amos, Ricky S. ; et al.	2005-08-25
High performance CMOS device structure with mid-gap metal gate Grant 6,916,698 - Mocuta , et al. July 12, 2	2005-07-12
Hybrid planar and finFET CMOS devices Grant 6,911,383 - Doris , et al. June 28, 2	2005-06-28
Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique App 20050116289 - Boyd, Diane C. ; et al.	2005-06-02
Ultra-thin Si MOSFET device structure and method of manufacture App 20050118826 - Boyd, Diane C. ; et al.	2005-06-02
Method and process to make multiple-threshold metal gates CMOS technology App 20050106788 - Amos, Ricky ; et al.	2005-05-19
Stressed Semiconductor Device Structures Having Granular Semiconductor Material App 20050106799 - Doris, Bruce B. ; et al.	2005-05-19
Oxidation Method For Altering A Film Structure And Cmos Transistor Structure Formed Therewith App 20050093081 - Belyansky, Michael P. ; et al.	2005-05-05
SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20050042841 - Boyd, Diane C. ; et al.	2005-02-24
Method and process to make multiple-threshold metal gates CMOS technology Grant 6,846,734 - Amos , et al. January 25, 2	2005-01-25
Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process Grant 6,841,831 - Hanafi , et al. January 11, 2	2005-01-11
HYBRID PLANAR AND FinFET CMOS DEVICES App 20040266076 - Doris, Bruce B. ; et al.	2004-12-30
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 6,835,633 - Boyd , et al. December 28, 2	2004-12-28
High performance CMOS device structure with mid-gap metal gate App 20040171205 - Mocuta, Anda C. ; et al.	2004-09-02
High performance CMOS device structure with mid-gap metal gate Grant 6,762,469 - Mocuta , et al. July 13, 2	2004-07-13
Method and process to make multiple-threshold metal gates CMOS technology App 20040094804 - Amos, Ricky ; et al.	2004-05-20
SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20040018699 - Boyd, Diane C. ; et al.	2004-01-29
Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region Grant 6,660,598 - Hanafi , et al. December 9, 2	2003-12-09
Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process App 20030211681 - Hanafi, Hussein I. ; et al.	2003-11-13
High performance CMOS device structure with mid-gap metal gate App 20030197230 - Mocuta, Anda C. ; et al.	2003-10-23
Method Of Forming A Fully-depleted Soi (silicon-on-insulator) Mosfet Having A Thinned Channel Region App 20030162358 - Hanafi, Hussein I. ; et al.	2003-08-28
Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme Grant 6,461,529 - Boyd , et al. October 8, 2	2002-10-08
Resist image reversal by means of spun-on-glass Grant 6,221,562 - Boyd , et al. April 24, 2	2001-04-24
Field effect transistors with improved implants and method for making such transistors Grant 6,143,635 - Boyd , et al. November 7, 2	2000-11-07
Method for making field effect transistors having sub-lithographic gates with vertical side walls Grant 6,040,214 - Boyd , et al. March 21, 2	2000-03-21
Method for varying x-ray hybrid resist space dimensions Grant 6,014,422 - Boyd , et al. January 11, 2	2000-01-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.