Bowonder; Anupama

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bowonder; Anupama.The latest application filed is for "epitaxial oxide plug for strained transistors".

Company Profile

12.11.16

Bowonder; Anupama - Portland OR
Bowonder; Anupama - Berkeley CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned gate edge architecture with alternate channel material Grant 11,456,357 - Guha , et al. September 27, 2	2022-09-27
Buried etch-stop layer to help control transistor source/drain depth Grant 11,430,868 - Mehandru , et al. August 30, 2	2022-08-30
Source or drain structures with contact etch stop layer Grant 11,374,100 - Bomberger , et al. June 28, 2	2022-06-28
Epitaxial Oxide Plug For Strained Transistors App 20220131007 - JAMBUNATHAN; Karthik ; et al.	2022-04-28
Epitaxial oxide plug for strained transistors Grant 11,251,302 - Jambunathan , et al. February 15, 2	2022-02-15
Semiconductor layer between source/drain regions and gate spacers Grant 11,152,461 - Mehandru , et al. October 19, 2	2021-10-19
Multiple Strain States In Epitaxial Transistor Channel Through The Incorporation Of Stress-relief Defects Within An Underlying Seed Material App 20210257492 - Lilak; Aaron ; et al.	2021-08-19
Transistors with channel and sub-channel regions with distinct compositions and dimensions Grant 11,069,795 - Jambunathan , et al. July 20, 2	2021-07-20
Fin Shaping And Integrated Circuit Structures Resulting Therefrom App 20210167209 - LIAO; Szuya S. ; et al.	2021-06-03
Fin Smoothing And Integrated Circuit Structures Resulting Therefrom App 20210167210 - BOMBERGER; Cory ; et al.	2021-06-03
Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices Grant 10,886,272 - Cea , et al. January 5, 2	2021-01-05
Sub-fin Leakage Reduction For Template Strained Materials App 20200411640 - MEHANDRU; Rishabh ; et al.	2020-12-31
Transistors With Channel And Sub-channel Regions With Distinct Compositions And Dimensions App 20200411513 - Jambunathan; Karthik ; et al.	2020-12-31
Epitaxial Oxide Plug For Strained Transistors App 20200220014 - Jambunathan; Karthik ; et al.	2020-07-09
Integrated Circuit Structures With Source Or Drain Dopant Diffusion Blocking Layers App 20200219975 - BOMBERGER; Cory ; et al.	2020-07-09
Integrated Circuit Structures Having Asymmetric Source And Drain Structures App 20200105759 - BOWONDER; Anupama ; et al.	2020-04-02
Channel Structures With Sub-fin Dopant Diffusion Blocking Layers App 20200006332 - BOMBERGER; Cory ; et al.	2020-01-02
Buried Etch-stop Layer To Help Control Transistor Source/drain Depth App 20200006488 - MEHANDRU; RISHABH ; et al.	2020-01-02
Self-aligned Gate Edge Architecture With Alternate Channel Material App 20200006487 - Guha; Biswajeet ; et al.	2020-01-02
Source Or Drain Structures With Contact Etch Stop Layer App 20200006504 - BOMBERGER; Cory ; et al.	2020-01-02
Source Or Drain Structures With Relatively High Germanium Content App 20200006491 - BOMBERGER; Cory ; et al.	2020-01-02
Semiconductor Layer Between Source/drain Regions And Gate Spacers App 20190355811 - Mehandru; Rishabh ; et al.	2019-11-21
Techniques For Forming Dual-strain Fins For Co-integrated N-mos And P-mos Devices App 20190326290 - CEA; STEPHEN M. ; et al.	2019-10-24
Tunneling transistor suitable for low voltage operation Grant 9,117,893 - Hu , et al. August 25, 2	2015-08-25
Tunneling transistor suitable for low voltage operation Grant 8,384,122 - Hu , et al. February 26, 2	2013-02-26

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