Bowman; Joshua W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bowman; Joshua W..The latest application filed is for "logical register recovery within a processor".

Company Profile

32.29.31

Bowman; Joshua W. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor Grant 11,403,109 - Battle , et al. August 2, 2	2022-08-02
Logical register recovery within a processor Grant 11,360,779 - Battle , et al. June 14, 2	2022-06-14
Instruction streaming using state migration Grant 11,301,254 - Battle , et al. April 12, 2	2022-04-12
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor Grant 11,194,578 - Battle , et al. December 7, 2	2021-12-07
System and handling of register data in processors Grant 11,188,332 - Battle , et al. November 30, 2	2021-11-30
Supporting speculative microprocessor instruction execution Grant 11,144,364 - Battle , et al. October 12, 2	2021-10-12
Register file write using pointers Grant 11,093,282 - Barrick , et al. August 17, 2	2021-08-17
High bandwidth logical register flush recovery Grant 11,068,267 - Battle , et al. July 20, 2	2021-07-20
Instruction streaming using copy select vector Grant 11,061,681 - Battle , et al. July 13, 2	2021-07-13
Logical Register Recovery Within A Processor App 20210089322 - Battle; Steven J. ; et al.	2021-03-25
System and handling of register data in processors Grant 10,956,158 - Battle , et al. March 23, 2	2021-03-23
Logical register recovery within a processor Grant 10,949,213 - Battle , et al. March 16, 2	2021-03-16
Instruction chaining Grant 10,936,321 - Feiste , et al. March 2, 2	2021-03-02
Issue queue snooping for asynchronous flush and restore of distributed history buffer Grant 10,909,034 - Terry , et al. February 2, 2	2021-02-02
Instruction Streaming Using State Migration App 20210026642 - Battle; Steven J. ; et al.	2021-01-28
Instruction Streaming Using Copy Select Vector App 20210026643 - Battle; Steven J. ; et al.	2021-01-28
System And Handling Of Register Data In Processors App 20200356366 - Battle; Steven J. ; et al.	2020-11-12
System And Handling Of Register Data In Processors App 20200356369 - Battle; Steven J. ; et al.	2020-11-12
High Bandwidth Logical Register Flush Recovery App 20200341767 - Battle; Steven J. ; et al.	2020-10-29
Register File Write Using Pointers App 20200326978 - Barrick; Brian D. ; et al.	2020-10-15
Flush-recovery bandwidth in a processor Grant 10,740,140 - Battle , et al. A	2020-08-11
Operation of a multi-slice processor implementing load-hit-store handling Grant 10,740,107 - Ayub , et al. A	2020-08-11
Instruction Chaining App 20200249954 - Kind Code	2020-08-06
Supporting Speculative Microprocessor Instruction Execution App 20200241931 - Battle; Steven J. ; et al.	2020-07-30
Merging status and control data in a reservation station Grant 10,719,056 - Barrick , et al.	2020-07-21
Logical Register Recovery Within A Processor App 20200183700 - Battle; Steven J. ; et al.	2020-06-11
Speculative Flush Recovery Lookup In A Processor App 20200183701 - Battle; Steven J. ; et al.	2020-06-11
Flush-recovery Bandwidth In A Processor App 20200159564 - Battle; Steven J. ; et al.	2020-05-21
Multi-level history buffer for transaction memory in a microprocessor Grant 10,545,765 - Barrick , et al. Ja	2020-01-28
Multiple Level History Buffer for Transaction Memory Support App 20200019405 - Battle; Steven J. ; et al.	2020-01-16
Fused Overloaded Register File Read to Enable 2-Cycle Move from Condition Register Instruction in a Microprocessor App 20190361698 - Battle; Steven J. ; et al.	2019-11-28
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor Grant 10,489,253 - Battle , et al. Nov	2019-11-26
Broadcasting messages between execution slices for issued instructions indicating when execution results are ready Grant 10,445,100 - Ayub , et al. Oc	2019-10-15
Asynchronous flush and restore of distributed history buffer Grant 10,379,867 - Terry , et al. A	2019-08-13
Issue Queue Snooping For Asynchronous Flush And Restore Of Distributed History Buffer App 20190188133 - TERRY; David R. ; et al.	2019-06-20
Asynchronous Flush And Restore Of Distributed History Buffer App 20190187995 - TERRY; David R. ; et al.	2019-06-20
Operation of a multi-slice processor implementing dependency accumulation instruction sequencing Grant 10,318,294 - Adeeb , et al.	2019-06-11
Direct register restore mechanism for distributed history buffers Grant 10,248,426 - Barrick , et al.	2019-04-02
Operation of a multi-slice processor with reduced flush and restore latency Grant 10,248,421 - Ayub , et al.	2019-04-02
Operation of a multi-slice processor with reduced flush and restore latency Grant 10,241,790 - Ayub , et al.	2019-03-26
On-demand Gpr Ecc Error Detection And Scrubbing For A Multi-slice Microprocessor App 20180336108 - BATTLE; Steven J. ; et al.	2018-11-22
Multi-level History Buffer For Transaction Memory In A Microprocessor App 20180336037 - BARRICK; Brian D. ; et al.	2018-11-22
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Grant 9,959,123 - Bowman , et al. May 1, 2	2018-05-01
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Grant 9,928,073 - Bowman , et al. March 27, 2	2018-03-27
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor Grant 9,921,833 - Bowman , et al. March 20, 2	2018-03-20
Operation Of A Multi-slice Processor Implementing Prioritized Dependency Chain Resolution App 20180004527 - ADEEB; KHANDKER N. ; et al.	2018-01-04
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor Grant 9,858,078 - Bowman , et al. January 2, 2	2018-01-02
Operation Of A Multi-slice Processor Implementing Dependency Accumulation Instruction Sequencing App 20170364358 - ADEEB; KHANDKER N. ; et al.	2017-12-21
Transmitting Data Between Execution Slices Of A Multi-slice Processor App 20170357513 - AYUB; SALMA ; et al.	2017-12-14
Operation Of A Multi-slice Processor Implementing Load-hit-store Handling App 20170351522 - AYUB; SALMA ; et al.	2017-12-07
Direct Register Restore Mechanism For Distributed History Buffers App 20170344380 - BARRICK; Brian D. ; et al.	2017-11-30
Merging Status And Control Data In A Reservation Station App 20170315528 - Barrick; Brian ; et al.	2017-11-02
Operation Of A Multi-slice Processor With Reduced Flush And Restore Latency App 20170168826 - AYUB; SALMA ; et al.	2017-06-15
Operation Of A Multi-slice Processor With Reduced Flush And Restore Latency App 20170168818 - AYUB; Salma ; et al.	2017-06-15
Operation Of A Multi-slice Processor With Speculative Data Loading App 20170168821 - BOWMAN; JOSHUA W. ; et al.	2017-06-15
Operation Of A Multi-slice Processor With Speculative Data Loading App 20170168836 - BOWMAN; JOSHUA W. ; et al.	2017-06-15
Parity protection of a register Grant 9,639,418 - Bowman , et al. May 2, 2	2017-05-02
Parity Protection Of A Register App 20170060673 - Bowman; Joshua W. ; et al.	2017-03-02
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor App 20160357566 - Bowman; Joshua W. ; et al.	2016-12-08
Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor App 20160357567 - Bowman; Joshua W. ; et al.	2016-12-08

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