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BOUTON; Guilhem Patent Filings

BOUTON; Guilhem

Patent Applications and Registrations

Patent applications and USPTO patent grants for BOUTON; Guilhem.The latest application filed is for "low-dispersion component in an electronic chip".

Company Profile
12.21.23
  • BOUTON; Guilhem - Peynier FR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Low-dispersion Component In An Electronic Chip
App 20220122910 - TAILLIET; Francois ;   et al.
2022-04-21
Low-dispersion component in an electronic chip
Grant 11,244,893 - Tailliet , et al. February 8, 2
2022-02-08
Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
Grant 10,861,802 - Rivero , et al. December 8, 2
2020-12-08
Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
Grant 10,770,547 - Bouton , et al. Sep
2020-09-08
MOS transistor with reduced hump effect
Grant 10,714,583 - Rivero , et al.
2020-07-14
Integrated Circuit Comprising Components, For Example Nmos Transistors, Having Active Regions With Relaxed Compressive Stresses
App 20200052073 - BOUTON; Guilhem ;   et al.
2020-02-13
Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
Grant 10,490,632 - Bouton , et al. Nov
2019-11-26
Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto
Grant 10,418,322 - Bouton , et al. Sept
2019-09-17
Integrated Circuit Comprising Components, For Example Nmos Transistors, Having Active Regions With Relaxed Compressive Stresses
App 20190165105 - BOUTON; Guilhem ;   et al.
2019-05-30
Method For Forming At Least One Electrical Discontinuity In An Integrated Circuit, And Corresponding Integrated Circuit
App 20190103369 - RIVERO; Christian ;   et al.
2019-04-04
Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
Grant 10,211,291 - Bouton , et al. Feb
2019-02-19
Mos Transistor With Reduced Hump Effect
App 20190027565 - RIVERO; Christian ;   et al.
2019-01-24
Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
Grant 10,177,101 - Rivero , et al. J
2019-01-08
Low-dispersion Component In An Electronic Chip
App 20180323141 - TAILLIET; Francois ;   et al.
2018-11-08
Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto
Grant 10,115,666 - Bouton , et al. October 30, 2
2018-10-30
Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit
Grant 10,049,991 - Rivero , et al. August 14, 2
2018-08-14
Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit
Grant 10,049,982 - Rivero , et al. August 14, 2
2018-08-14
Low-dispersion component in an electronic chip
Grant 10,043,741 - Tailliet , et al. August 7, 2
2018-08-07
Method For Forming At Least One Electrical Discontinuity In An Integrated Circuit, And Corresponding Integrated Circuit
App 20180145040 - Rivero; Christian ;   et al.
2018-05-24
Method For Forming At Least One Electrical Discontinuity In An Interconnection Part Of An Integrated Circuit Without Addition Of Additional Material, And Corresponding Integrated Circuit
App 20180145027 - Rivero; Christian ;   et al.
2018-05-24
Method For Forming At Least One Electrical Discontinuity In An Interconnection Part Of An Integrated Circuit, And Corresponding Integrated Circuit
App 20180145039 - Rivero; Christian ;   et al.
2018-05-24
Integrated Circuit Comprising Components, For Example Nmos Transistors, Having Active Regions With Relaxed Compressive Stresses
App 20180130881 - Bouton; Guilhem ;   et al.
2018-05-10
Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
Grant 9,899,476 - Bouton , et al. February 20, 2
2018-02-20
Low-dispersion Component In An Electronic Chip
App 20170373001 - Tailliet; Francois ;   et al.
2017-12-28
Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
Grant 9,780,045 - Fornara , et al. October 3, 2
2017-10-03
Method For Fabrication Of An Integrated Circuit Rendering A Reverse Engineering Of The Integrated Circuit More Difficult And Corresponding Integrated Circuit
App 20170194267 - Fornara; Pascal ;   et al.
2017-07-06
Integrated Circuit Comprising Components, For Example Nmos Transistors, Having Active Regions With Relaxed Compressive Stresses
App 20160093696 - Bouton; Guilhem ;   et al.
2016-03-31
Method For Making A Photolithography Mask Intended For The Formation Of Contacts, Mask And Integrated Circuit Corresponding Thereto
App 20160086883 - BOUTON; GUILHEM ;   et al.
2016-03-24
Method For Fabrication Of An Integrated Circuit Rendering A Reverse Engineering Of The Integrated Circuit More Difficult And Corresponding Integrated Circuit
App 20160064339 - Fornara; Pascal ;   et al.
2016-03-03
Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
Grant 9,269,771 - Rivero , et al. February 23, 2
2016-02-23
Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method
Grant 9,263,518 - Rivero , et al. February 16, 2
2016-02-16
Component, For Example Nmos Transistor, With An Active Region Under Relaxed Compressive Stress, And Associated Decoupling Capacitor
App 20150340426 - Wuidart; Sylvie ;   et al.
2015-11-26
Component, For Example Nmos Transistor, With Active Region With Relaxed Compression Stresses, And Fabrication Method
App 20150255540 - Bouton; Guilhem ;   et al.
2015-09-10
Integrated Circuit Comprising Components, For Example Nmos Transistors, Having Active Regions With Relaxed Compressive Stresses
App 20150249132 - Rivero; Christian ;   et al.
2015-09-03
Process for fabricating an integrated circuit comprising an analog block and a digital block, and corresponding integrated circuit
Grant 8,914,756 - Bouton December 16, 2
2014-12-16
Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuit
Grant 8,881,090 - Bouton , et al. November 4, 2
2014-11-04
Method For Making A Photolithography Mask Intended For The Formation Of Contacts, Mask And Integrated Circuit Corresponding Thereto
App 20140291858 - BOUTON; Guilhem ;   et al.
2014-10-02
Method For Fabrication Of An Integrated Circuit In A Technology Reduced With Respect To A Native Technology, And Corresponding Integrated Circuit
App 20130181294 - BOUTON; Guilhem ;   et al.
2013-07-18
Process For Fabricating An Integrated Circuit Comprising An Analog Block And A Digital Block, And Corresponding Integrated Circuit
App 20120104632 - BOUTON; Guilhem
2012-05-03
Chip differentiation at the level of a reticle
Grant 6,780,716 - Wuidart , et al. August 24, 2
2004-08-24
Chip differentiation at the level of a reticle
App 20030181025 - Wuidart, Luc ;   et al.
2003-09-25

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