loadpatents
name:-0.0025448799133301
name:-0.015958070755005
name:-0.00047612190246582
Boury; Bechara F. Patent Filings

Boury; Bechara F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Boury; Bechara F..The latest application filed is for "computing device with asynchronous auxiliary execution unit".

Company Profile
0.15.1
  • Boury; Bechara F. - Raleigh NC
  • Boury; Bechara F. - Boca Raton FL
  • Boury; Bechara F. - Milpitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Computing device with asynchronous auxiliary execution unit
Grant 9,201,801 - Boury , et al. December 1, 2
2015-12-01
Computing Device with Asynchronous Auxiliary Execution Unit
App 20120066483 - Boury; Bechara F. ;   et al.
2012-03-15
Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
Grant 5,621,897 - Boury , et al. April 15, 1
1997-04-15
Power management of DMA slaves with DMA traps
Grant 5,619,729 - Bland , et al. April 8, 1
1997-04-08
Dynamic bus sizing of DMA transfers
Grant 5,548,786 - Amini , et al. August 20, 1
1996-08-20
System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus
Grant 5,544,346 - Amini , et al. August 6, 1
1996-08-06
Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
Grant 5,499,346 - Amini , et al. March 12, 1
1996-03-12
System direct memory access (DMA) support logic for PCI based computer system
Grant 5,450,551 - Amini , et al. September 12, 1
1995-09-12
Arbitration logic for multiple bus computer system
Grant 5,396,602 - Amini , et al. March 7, 1
1995-03-07
DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
Grant 5,381,538 - Amini , et al. January 10, 1
1995-01-10
Error detection and recovery in a DMA controller
Grant 5,333,274 - Amini , et al. July 26, 1
1994-07-26
Parity error detection and recovery
Grant 5,313,627 - Amini , et al. May 17, 1
1994-05-17
Controlling bus allocation using arbitration hold
Grant 5,301,282 - Amini , et al. April 5, 1
1994-04-05
Arbitration control logic for computer system having dual bus architecture
Grant 5,265,211 - Amini , et al. November 23, 1
1993-11-23
CPU bus allocation control
Grant 5,239,631 - Boury , et al. August 24, 1
1993-08-24

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