Boudon; Gerard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Boudon; Gerard.The latest application filed is for "self-synchronizing bit error analyzer and circuit".

Company Profile

0.6.3

Boudon; Gerard - Mennecy FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-synchronizing bit error analyzer and circuit Grant 7,661,039 - Boudon , et al. February 9, 2	2010-02-09
Self-synchronizing bit error analyzer and circuit App 20090019326 - Boudon; Gerard ; et al.	2009-01-15
Self-synchronising bit error analyser and circuit Grant 7,404,115 - Boudon , et al. July 22, 2	2008-07-22
Self-synchronising Bit Error Analyser And Circuit App 20070011534 - Boudon; Gerard ; et al.	2007-01-11
An Improved Fifo Based Controller Circuit For Slave Devices Attached To A Cpu Bus App 20040123004 - Boudon, Gerard ; et al.	2004-06-24
Interrupt masker for an interrupt handler with double-edge interrupt request signals detection Grant 6,219,744 - Bredin , et al. April 17, 2	2001-04-17
Latch cell family in CMOS technology gate array Grant 4,988,893 - Bonneau , et al. January 29, 1	1991-01-29
Logic circuits for forming VLSI logic networks Grant 4,950,927 - Boudon , et al. August 21, 1	1990-08-21
Decoding and selection circuit for a monolithic memory Grant 4,394,752 - Boudon , et al. July 19, 1	1983-07-19

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