loadpatents
name:-0.015581846237183
name:-0.064337968826294
name:-0.00045108795166016
Bothra; Subhas Patent Filings

Bothra; Subhas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bothra; Subhas.The latest application filed is for "fully differential, high q, on-chip, impedance matching section".

Company Profile
0.57.12
  • Bothra; Subhas - Fremont CA
  • Bothra; Subhas - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Fully differential, high Q, on-chip, impedance matching section
Grant 8,274,353 - Barrett , et al. September 25, 2
2012-09-25
System and method allowing for safe use of a headset
Grant 8,270,629 - Bothra , et al. September 18, 2
2012-09-18
Fully Differential, High Q, On-Chip, Impedance Matching Section
App 20110163831 - Barrett; Carol ;   et al.
2011-07-07
Fully differential, high Q, on-chip, impedance matching section
Grant 7,911,310 - Barrett , et al. March 22, 2
2011-03-22
Method to implement metal fill during integrated circuit design and layout
Grant 7,614,024 - Bothra November 3, 2
2009-11-03
Fully Differential, High Q, On-Chip, Impedance Matching Section
App 20090127654 - Barrett; Carol ;   et al.
2009-05-21
Fully differential, high Q, on-chip, impedance matching section
Grant 7,489,221 - Barrett , et al. February 10, 2
2009-02-10
I/O driver power distribution method for reducing silicon area
Grant 7,434,189 - Baumann , et al. October 7, 2
2008-10-07
Power supply integration for low power single chip RF CMOS solutions for use in battery operated electronic devices
App 20070210775 - Bothra; Subhas ;   et al.
2007-09-13
System and method allowing for safe use of a headset
App 20070092087 - Bothra; Subhas ;   et al.
2007-04-26
I/O driver power distribution method for reducing silicon area
App 20070090401 - Baumann; Donald ;   et al.
2007-04-26
Method to implement metal fill during integrated circuit design and layout
App 20070083833 - Bothra; Subhas
2007-04-12
Fully differential, high Q, on-chip, impedance matching section
App 20060273874 - Barrett; Carol ;   et al.
2006-12-07
Fully differential, high Q, on-chip, impedance matching section
Grant 7,095,307 - Barrett , et al. August 22, 2
2006-08-22
Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection
Grant 6,916,525 - Bothra , et al. July 12, 2
2005-07-12
Pad metallization over active circuitry
Grant 6,787,908 - Skala , et al. September 7, 2
2004-09-07
Semiconductor pressure transducer structures and methods for making the same
Grant 6,756,316 - Bothra , et al. June 29, 2
2004-06-29
Semiconductor inductor and methods for making the same
Grant 6,717,232 - Bothra April 6, 2
2004-04-06
Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection
App 20040058543 - Bothra, Subhas ;   et al.
2004-03-25
Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit
Grant 6,710,425 - Bothra March 23, 2
2004-03-23
Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection
Grant 6,649,253 - Bothra , et al. November 18, 2
2003-11-18
Semiconductor inductor and methods for making the same
App 20030170989 - Bothra, Subhas
2003-09-11
Methods for making semiconductor inductor
Grant 6,573,148 - Bothra June 3, 2
2003-06-03
Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
Grant 6,569,757 - Weling , et al. May 27, 2
2003-05-27
Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications
Grant 6,545,338 - Bothra , et al. April 8, 2
2003-04-08
Structure and method to increase density of MIM capacitors in damascene process
App 20020192919 - Bothra, Subhas
2002-12-19
Seal ring structure for IC containing integrated digital/RF/analog circuits and functions
Grant 6,492,716 - Bothra , et al. December 10, 2
2002-12-10
Modified optics for imaging of lens limited subresolution features
Grant 6,411,367 - Baker , et al. June 25, 2
2002-06-25
Process to control poly silicon profiles in a dual doped poly silicon process
Grant 6,399,432 - Zheng , et al. June 4, 2
2002-06-04
Method for reducing the capacitance between interconnects by forming voids in dielectric material
Grant 6,387,797 - Bothra , et al. May 14, 2
2002-05-14
Use of optimized film stacks for increasing absorption for laser repair of fuse links
Grant 6,372,522 - Weling , et al. April 16, 2
2002-04-16
Automated design of on-chip capacitive structures for suppressing inductive noise
Grant 6,327,695 - Bothra , et al. December 4, 2
2001-12-04
Intelligent gate-level fill methods for reducing global pattern density effects
Grant 6,323,113 - Gabriel , et al. November 27, 2
2001-11-27
Method for determining nitrogen concentration in a film of nitrided oxide material
Grant 6,313,466 - Olsen , et al. November 6, 2
2001-11-06
Process to improve adhesion of PECVD cap layers in integrated circuits
Grant 6,303,192 - Annapragada , et al. October 16, 2
2001-10-16
Pad metallization over active circuitry
App 20010026018 - Skala, Stephen L. ;   et al.
2001-10-04
Air gap dielectric in self-aligned via structures
Grant 6,281,585 - Bothra August 28, 2
2001-08-28
Methods and apparatus for design rule checking
Grant 6,275,971 - Levy , et al. August 14, 2
2001-08-14
Reduced gate length transistor structures and methods for fabricating the same
App 20010009792 - Bothra, Subhas ;   et al.
2001-07-26
Electromigration impeding composite metallization lines and methods for making the same
Grant 6,191,481 - Bothra , et al. February 20, 2
2001-02-20
Design level optical proximity correction methods
Grant 6,189,136 - Bothra February 13, 2
2001-02-13
Methods of forming a semiconductor device
Grant 6,176,983 - Bothra , et al. January 23, 2
2001-01-23
Electromigration bonding process and system
Grant 6,156,626 - Bothra December 5, 2
2000-12-05
Method for preventing electrochemical erosion of interconnect structures
Grant 6,153,531 - Bothra , et al. November 28, 2
2000-11-28
Programmable semiconductor structures and methods for making the same
Grant 6,143,642 - Sur, Jr. , et al. November 7, 2
2000-11-07
Method for forming vias through porous dielectric material and devices formed thereby
Grant 6,140,221 - Annapragada , et al. October 31, 2
2000-10-31
Process for making self-aligned conductive via structures
Grant 6,133,635 - Bothra , et al. October 17, 2
2000-10-17
Method of making photo alignment structure
Grant 6,133,111 - Sur , et al. October 17, 2
2000-10-17
Semiconductor manufacturing apparatus and method for measuring in-situ pressure across a wafer
Grant 6,129,613 - Bothra October 10, 2
2000-10-10
Micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system
Grant 6,127,811 - Shenoy , et al. October 3, 2
2000-10-03
Methods for making semiconductor devices having air dielectric interconnect structures
Grant 6,057,224 - Bothra , et al. May 2, 2
2000-05-02
Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die
Grant 6,030,885 - Bothra February 29, 2
2000-02-29
Composite metallization structures for improved post bonding reliability
Grant 6,020,647 - Skala , et al. February 1, 2
2000-02-01
Apparatus for automated pillar layout and method for implementing same
Grant 6,013,536 - Nowak , et al. January 11, 2
2000-01-11
Process for manufacturing ultra-sharp atomic force microscope (AFM) and scanning tunneling microscope (STM) tips
Grant 5,965,218 - Bothra , et al. October 12, 1
1999-10-12
Use of dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing
Grant 5,965,941 - Weling , et al. October 12, 1
1999-10-12
Parasitic resistance measuring device
Grant 5,933,020 - Bothra August 3, 1
1999-08-03
Methods and apparatus for polishing wafers
Grant 5,916,016 - Bothra June 29, 1
1999-06-29
Method for producing deep submicron interconnect vias
Grant 5,915,203 - Sengupta , et al. June 22, 1
1999-06-22
Reliable interconnect via structures and methods for making the same
Grant 5,913,141 - Bothra June 15, 1
1999-06-15
Micro-electromechanical voltage shifter
Grant 5,889,389 - Bothra , et al. March 30, 1
1999-03-30
Low power programmable fuse structures and methods for making the same
Grant 5,882,998 - Sur, Jr. , et al. March 16, 1
1999-03-16
Method for making devices having thin load structures
Grant 5,882,997 - Sur, Jr. , et al. March 16, 1
1999-03-16
Moisture barrier gap fill structure and method for making the same
Grant 5,880,519 - Bothra , et al. March 9, 1
1999-03-09
Photo alignment structure
Grant 5,877,562 - Sur , et al. March 2, 1
1999-03-02
Method of making high resistive structures in salicided process semiconductor devices
Grant 5,834,356 - Bothra , et al. November 10, 1
1998-11-10
Integrated circuit structure having an air dielectric and dielectric support pillars
Grant 5,798,559 - Bothra , et al. August 25, 1
1998-08-25
Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing
Grant 5,639,697 - Weling , et al. June 17, 1
1997-06-17
Method of making microscope probe tips
Grant 5,540,958 - Bothra , et al. July 30, 1
1996-07-30

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed