Borer; Terry

Patent Applications and Registrations

Patent applications and USPTO patent grants for Borer; Terry.The latest application filed is for "method and apparatus for implementing soft constraints in tools used for designing programmable logic devices".

Company Profile

0.21.2

Borer; Terry - Toronto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20170337318 - Borer; Terry ; et al.	2017-11-23
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 9,754,065 - Borer , et al. September 5, 2	2017-09-05
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20140047405 - Borer; Terry ; et al.	2014-02-13
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 8,589,849 - Borer , et al. November 19, 2	2013-11-19
M/A for performing incremental compilation using top-down and bottom-up design approaches Grant 8,589,838 - Borer , et al. November 19, 2	2013-11-19
Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow Grant 8,370,776 - Chan , et al. February 5, 2	2013-02-05
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 8,250,505 - Borer , et al. August 21, 2	2012-08-21
Directed design space exploration Grant 8,037,435 - Chesal , et al. October 11, 2	2011-10-11
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 7,669,157 - Borer , et al. February 23, 2	2010-02-23
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,594,208 - Borer , et al. September 22, 2	2009-09-22
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays Grant 7,594,204 - Singh , et al. September 22, 2	2009-09-22
Method and apparatus for performing incremental compilation Grant 7,464,362 - Borer , et al. December 9, 2	2008-12-09
Method and apparatus for performing compound duplication of components on field programmable gate arrays Grant 7,401,314 - Schabas , et al. July 15, 2	2008-07-15
Techniques for editing circuit design files to be compatible with a new programmable IC Grant 7,389,489 - Chesal , et al. June 17, 2	2008-06-17
Directed design space exploration Grant 7,370,295 - Chesal , et al. May 6, 2	2008-05-06
Method and apparatus for performing retiming on field programmable gate arrays Grant 7,360,190 - Singh , et al. April 15, 2	2008-04-15
Leveraging combinations of synthesis, placement and incremental optimizations Grant 7,290,240 - Lam-Leventis , et al. October 30, 2	2007-10-30
Method and apparatus for performing logic replication in field programmable gate arrays Grant 7,257,800 - Singh , et al. August 14, 2	2007-08-14
Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis Grant 7,254,801 - Borer , et al. August 7, 2	2007-08-07
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,181,703 - Borer , et al. February 20, 2	2007-02-20

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