Bonser; Douglas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bonser; Douglas.The latest application filed is for "formation of finfet gate spacer".

Company Profile

0.11.6

Bonser; Douglas - Hopewell Junction NY US
Bonser; Douglas - Austin TX
Bonser; Douglas - Irving TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Formation of FinFET gate spacer Grant 8,525,234 - Bonser , et al. September 3, 2	2013-09-03
Methods for fabricating FinFET semiconductor devices using planarized spacers Grant 8,268,727 - Johnson , et al. September 18, 2	2012-09-18
Formation Of Finfet Gate Spacer App 20120168833 - BONSER; Douglas ; et al.	2012-07-05
Formation of FinFET gate spacer Grant 8,174,055 - Bonser , et al. May 8, 2	2012-05-08
Formation Of Finfet Gate Spacer App 20110198673 - Bonser; Douglas ; et al.	2011-08-18
Method for fabricating a semiconductor device having a semiconductive resistor structure Grant 7,985,639 - Johnson , et al. July 26, 2	2011-07-26
Method For Fabricating A Semiconductor Device Having A Semiconductive Resistor Structure App 20110070712 - JOHNSON; Frank Scott ; et al.	2011-03-24
Methods For Fabricating Finfet Semiconductor Devices Using Planarized Spacers App 20100267238 - Johnson; Frank S. ; et al.	2010-10-21
Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions Grant 7,279,386 - Kelling , et al. October 9, 2	2007-10-09
Method of forming isolation trench with spacer formation Grant 7,144,785 - Dakshina-Murthy , et al. December 5, 2	2006-12-05
Selective epitaxial growth for tunable channel thickness Grant 7,105,399 - Dakshina-Murthy , et al. September 12, 2	2006-09-12
Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions App 20060121711 - Kelling; Mark C. ; et al.	2006-06-08
Method of forming isolation trench with spacer formation App 20060094205 - Dakshina-Murthy; Srikanteswara ; et al.	2006-05-04
CVD silicon carbide layer as a BARC and hard mask for gate patterning Grant 6,653,735 - Yang , et al. November 25, 2	2003-11-25
Method and apparatus for control of critical dimension using feedback etch control Grant 6,245,581 - Bonser , et al. June 12, 2	2001-06-12
Arrangement system for object placement on windows Grant 5,883,625 - Crawford , et al. March 16, 1	1999-03-16

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