Bonella; Randy M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bonella; Randy M..The latest application filed is for "advanced dynamic disk memory module".

Company Profile

0.26.9

Bonella; Randy M. - Portland OR
Bonella; Randy M. - Cypress TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells Grant 7,941,592 - Bonella , et al. May 10, 2	2011-05-10
Advanced Dynamic Disk Memory Module App 20100223422 - Bonella; Randy M. ; et al.	2010-09-02
Advanced dynamic disk memory module Grant 7,681,004 - Bonella , et al. March 16, 2	2010-03-16
Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells App 20100042772 - Bonella; Randy M. ; et al.	2010-02-18
Buffering and interleaving data transfer between a chipset and memory modules Grant 7,249,232 - Halbert , et al. July 24, 2	2007-07-24
Advanced dynamic disk memory module special operations App 20070136523 - Bonella; Randy M. ; et al.	2007-06-14
Advanced dynamic disk memory module App 20070079065 - Bonella; Randy M. ; et al.	2007-04-05
Dual-port buffer-to-memory interface Grant 7,024,518 - Halbert , et al. April 4, 2	2006-04-04
Digital system of adjusting delays on circuit boards Grant 6,928,571 - Bonella , et al. August 9, 2	2005-08-09
Memory module and memory component built-in self test Grant 6,928,593 - Halbert , et al. August 9, 2	2005-08-09
Buffering data transfer between a chipset and memory modules Grant 6,820,163 - McCall , et al. November 16, 2	2004-11-16
Buffering and interleaving data transfer between a chipset and memory modules App 20040188704 - Halbert, John B. ; et al.	2004-09-30
Memory module having buffer for isolating stacked memory devices Grant 6,747,887 - Halbert , et al. June 8, 2	2004-06-08
Dual-port buffer-to-memory interface Grant 6,742,098 - Halbert , et al. May 25, 2	2004-05-25
Buffering and interleaving data transfer between a chipset and memory modules Grant 6,697,888 - Halbert , et al. February 24, 2	2004-02-24
Multi-tier point-to-point ring memory interface Grant 6,658,509 - Bonella , et al. December 2, 2	2003-12-02
Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing Grant 6,625,687 - Halbert , et al. September 23, 2	2003-09-23
Buffer to multiply memory interface Grant 6,553,450 - Dodd , et al. April 22, 2	2003-04-22
System and method for providing reliable transmission in a buffered memory system Grant 6,530,006 - Dodd , et al. March 4, 2	2003-03-04
Memory module having buffer for isolating stacked memory devices App 20030035312 - Halbert, John B. ; et al.	2003-02-20
Multi-tier point-to-point buffered memory interface Grant 6,493,250 - Halbert , et al. December 10, 2	2002-12-10
Memory module having buffer for isolating stacked memory devices Grant 6,487,102 - Halbert , et al. November 26, 2	2002-11-26
Memory interface having source-synchronous command/address signaling Grant 6,449,213 - Dodd , et al. September 10, 2	2002-09-10
Dual-port buffer-to-memory interface App 20020112119 - Halbert, John B. ; et al.	2002-08-15
Multi-tier Point-to-point Buffered Memory Interface App 20020084458 - Halbert, John B. ; et al.	2002-07-04
Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules Grant 6,317,352 - Halbert , et al. November 13, 2	2001-11-13
Method and apparatus for retrieving data from a data storage device App 20010011317 - Bonella, Randy M. ; et al.	2001-08-02
Bus master arbitration circuitry having improved prioritization Grant 5,797,020 - Bonella , et al. August 18, 1	1998-08-18
Circuit for selectively preventing a microprocessor from posting write cycles Grant 5,625,824 - Melo , et al. April 29, 1	1997-04-29
Fully pipelined and highly concurrent memory controller Grant 5,537,555 - Landry , et al. July 16, 1	1996-07-16
Bus master arbitration circuitry having improved prioritization Grant 5,471,590 - Melo , et al. November 28, 1	1995-11-28
Cache snoop latency prevention apparatus Grant 5,446,863 - Stevens , et al. August 29, 1	1995-08-29
Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle Grant 5,404,559 - Bonella , et al. April 4, 1	1995-04-04
Multiple input frequency memory controller Grant 5,333,293 - Bonella July 26, 1	1994-07-26
Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line Grant 5,325,503 - Stevens , et al. June 28, 1	1994-06-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.