Bokharey; Zuhair

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bokharey; Zuhair.The latest application filed is for "ic package design and methodology to compensate for die-substrate cte mismatch at reflow temperatures".

Company Profile

3.10.19

Bokharey; Zuhair - Santa Clara CA
Bokharey; Zuhair - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Ic Package Design And Methodology To Compensate For Die-substrate Cte Mismatch At Reflow Temperatures App 20210151403 - Chipalkatti; Jayprakash ; et al.	2021-05-20
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures Grant 10,943,882 - Chipalkatti , et al. March 9, 2	2021-03-09
Ic Package Design And Methodology To Compensate For Die-substrate Cte Mismatch At Reflow Temperatures App 20210066227 - Chipalkatti; Jayprakash ; et al.	2021-03-04
Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate Grant 10,219,387 - Zhang , et al. Feb	2019-02-26
Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad Grant 9,760,132 - Zhang , et al. September 12, 2	2017-09-12
Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity Grant 9,716,051 - Zhang , et al. July 25, 2	2017-07-25
Offset integrated circuit packaging interconnects Grant 9,478,482 - Zhang , et al. October 25, 2	2016-10-25
Variable-size solder bump structures for integrated circuit packaging Grant 9,385,098 - Zhang , et al. July 5, 2	2016-07-05
Absorbing excess under-fill flow with a solder trench Grant 9,368,422 - Zhang , et al. June 14, 2	2016-06-14
Substrate build up layer to achieve both finer design rule and better package coplanarity Grant 9,368,439 - Zhang , et al. June 14, 2	2016-06-14
System, method, and computer program product for affixing a post to a substrate pad Grant 9,087,830 - Zhang , et al. July 21, 2	2015-07-21
Stiffening Electronic Packages App 20150077918 - Zhang; Leilei ; et al.	2015-03-19
Process For Manufacturing A Printed Circuit Board Having High Density Microvias Formed In A Thick Substrate App 20140208590 - Zhang; Leilei ; et al.	2014-07-31
Absorbing Excess Under-fill Flow With A Solder Trench App 20140175681 - ZHANG; Leilei ; et al.	2014-06-26
Offset Integrated Circuit Packaging Interconnects App 20140138824 - Zhang; Leilei ; et al.	2014-05-22
Variable-size Solder Bump Structures For Integrated Circuit Packaging App 20140138823 - ZHANG; Leilei ; et al.	2014-05-22
Substrate Build Up Layer To Achieve Both Finer Design Rule And Better Package Coplanarity App 20140124944 - ZHANG; Leilei ; et al.	2014-05-08
Non-solder Mask Defined Copper Pad And Embedded Copper Pad To Reduce Packaging System Height App 20140124254 - ZHANG; Leilei ; et al.	2014-05-08
Open Solder Mask And Or Dielectric To Increase Lid Or Ring Thickness And Contact Area To Improve Package Coplanarity App 20140124913 - Zhang; Leilei ; et al.	2014-05-08
Reduced Integrated Circuit Package Lid Height App 20140117527 - Zhang; Leilei ; et al.	2014-05-01
Packaging Substrate With Reliable Via Structure App 20130313720 - ZHANG; Leilei ; et al.	2013-11-28
System, Method, And Computer Program Product For Preparing A Substrate Post App 20130256873 - Zhang; Leilei ; et al.	2013-10-03
System, Method, And Computer Program Product For Controlling Warping Of A Substrate App 20130251967 - Zhang; Leilei ; et al.	2013-09-26
System, Method, And Computer Program Product For Affixing A Post To A Substrate Pad App 20130252414 - Zhang; Leilei ; et al.	2013-09-26

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