BOHR; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for BOHR; Mark.The latest application filed is for "device, system and method for providing inductor structures".

Company Profile

24.61.80

BOHR; Mark - Aloha OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device, System And Method For Providing Inductor Structures App 20220302051 - GOMES; Wilfred ; et al.	2022-09-22
Deep Trench Via For Three-dimensional Integrated Circuit App 20220285342 - WANG; Yih ; et al.	2022-09-08
Device, Method And System For Providing A Stacked Arrangement Of Integrated Circuit Dies App 20220271022 - GOMES; Wilfred ; et al.	2022-08-25
Device layer interconnects Grant 11,410,928 - Bohr , et al. August 9, 2	2022-08-09
Device, system and method for providing inductor structures Grant 11,387,198 - Gomes , et al. July 12, 2	2022-07-12
Deep trench via for three-dimensional integrated circuit Grant 11,373,999 - Wang , et al. June 28, 2	2022-06-28
Device, method and system for providing a stacked arrangement of integrated circuit dies Grant 11,373,987 - Gomes , et al. June 28, 2	2022-06-28
Copper-filled Trench Contact For Transistor Performance Improvement App 20220115505 - KUHN; Kelin J. ; et al.	2022-04-14
Designs And Methods For Conductive Bumps App 20220059484 - DUBIN; Valery M. ; et al.	2022-02-24
High density and fine pitch interconnect structures in an electric test apparatus Grant 11,249,113 - Tadayon , et al. February 15, 2	2022-02-15
Designs and methods for conductive bumps Grant 11,201,129 - Dubin , et al. December 14, 2	2021-12-14
Gate Contact Structure Over Active Gate And Method To Fabricate Same App 20210210385 - PETHE; Abhijit Jayant ; et al.	2021-07-08
Gate contact structure over active gate and method to fabricate same Grant 11,004,739 - Pethe , et al. May 11, 2	2021-05-11
High Density And Fine Pitch Interconnect Structures In An Electric Test Apparatus App 20210088554 - Tadayon; Pooya ; et al.	2021-03-25
Device, Method And System For Providing A Stacked Arrangement Of Integrated Circuit Dies App 20210074695 - GOMES; Wilfred ; et al.	2021-03-11
Package On Active Silicon Semiconductor Packages App 20210013188 - Gomes; Wilfred ; et al.	2021-01-14
High density and fine pitch interconnect structures in an electric test apparatus Grant 10,877,068 - Tadayon , et al. December 29, 2	2020-12-29
Substrate-less Finfet Diode Architectures With Backside Metal Contact And Subfin Regions App 20200403007 - THOMSON; Nicholas ; et al.	2020-12-24
Self-aligned Gate Edge And Local Interconnect App 20200388675 - WEBB; Milton Clair ; et al.	2020-12-10
Self-aligned gate edge and local interconnect Grant 10,790,354 - Webb , et al. September 29, 2	2020-09-29
Device, System And Method For Providing Inductor Structures App 20200258852 - A1	2020-08-13
Die Interconnection Scheme For Providing A High Yielding Process For High Performance Microprocessors App 20200211970 - GOMES; Wilfred ; et al.	2020-07-02
Random-access Memory With Loaded Capacitance App 20200135266 - Kumar; Raghavan ; et al.	2020-04-30
Integrated Circuit Structures Having Asymmetric Source And Drain Structures App 20200105759 - BOWONDER; Anupama ; et al.	2020-04-02
Structures And Methods For Large Integrated Circuit Dies App 20200058646 - Gomes; Wilfred ; et al.	2020-02-20
High Density And Fine Pitch Interconnect Structures In An Electric Test Apparatus App 20200025801 - Tadayon; Pooya ; et al.	2020-01-23
Deep Trench Via For Three-dimensional Integrated Circuit App 20190378836 - WANG; Yih ; et al.	2019-12-12
Device Layer Interconnects App 20190378790 - Bohr; Mark ; et al.	2019-12-12
High density and fine pitch interconnect structures in an electric test apparatus Grant 10,488,438 - Tadayon , et al. Nov	2019-11-26
Self-aligned Gate Edge And Local Interconnect And Method To Fabricate Same App 20190326391 - WEBB; Milton Clair ; et al.	2019-10-24
High Density And Fine Pitch Interconnect Structures In An Electric Test Apparatus App 20190212366 - Tadayon; Pooya ; et al.	2019-07-11
Designs And Methods For Conductive Bumps App 20190198472 - DUBIN; Valery M. ; et al.	2019-06-27
Self-aligned gate edge and local interconnect and method to fabricate same Grant 10,319,812 - Webb , et al.	2019-06-11
Gate Contact Structure Over Active Gate And Method To Fabricate Same App 20190115257 - PETHE; Abhijit Jayant ; et al.	2019-04-18
Designs and methods for conductive bumps Grant 10,249,588 - Dubin , et al.	2019-04-02
Gate contact structure over active gate and method to fabricate same Grant 10,192,783 - Pethe , et al. Ja	2019-01-29
Self-aligned Gate Edge And Local Interconnect And Method To Fabricate Same App 20180047808 - WEBB; Milton Clair ; et al.	2018-02-15
Self-aligned gate edge and local interconnect and method to fabricate same Grant 9,831,306 - Webb , et al. November 28, 2	2017-11-28
Copper-filled Trench Contact For Transistor Performance Improvement App 20170263721 - KUHN; KELIN J. ; et al.	2017-09-14
Designs And Methods For Conductive Bumps App 20170084564 - DUBIN; Valery M. ; et al.	2017-03-23
Designs and methods for conductive bumps Grant 9,543,261 - Dubin , et al. January 10, 2	2017-01-10
Gate Contact Structure Over Active Gate And Method To Fabricate Same App 20170004998 - Pethe; Abhijit Jayant ; et al.	2017-01-05
Gate contact structure over active gate and method to fabricate same Grant 9,461,143 - Pethe , et al. October 4, 2	2016-10-04
Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same App 20160233298 - WEBB; Milton C. ; et al.	2016-08-11
Composite Materials For Use In Semiconductor Components App 20150187900 - Shankar; Sadasivan ; et al.	2015-07-02
Copper-filled Trench Contact For Transistor Performance Improvement App 20140264879 - Kuhn; Kelin J. ; et al.	2014-09-18
Copper-filled trench contact for transistor performance improvement Grant 8,766,372 - Kuhn , et al. July 1, 2	2014-07-01
Gate Contact Structure Over Active Gate And Method To Fabricate Same App 20140077305 - Pethe; Abhijit Jayant ; et al.	2014-03-20
Designs and methods for conductive bumps Grant 8,580,679 - Dubin , et al. November 12, 2	2013-11-12
Methods of forming electromigration and thermal gradient based fuse structures Grant 8,368,171 - Maiz , et al. February 5, 2	2013-02-05
Copper-filled Trench Contact For Transistor Performance Improvement App 20120299069 - Kuhn; Kelin J. ; et al.	2012-11-29
Copper-filled trench contact for transistor performance improvement Grant 8,258,057 - Kuhn , et al. September 4, 2	2012-09-04
Selective spacer formation on transistors of different classes on the same device Grant 8,174,060 - Curello , et al. May 8, 2	2012-05-08
Selective spacer formation on transistors of different classes on the same device Grant 8,154,067 - Curello , et al. April 10, 2	2012-04-10
Selective Spacer Formation On Transistors Of Different Classes On The Same Device App 20110157854 - Curello; Giuseppe ; et al.	2011-06-30
Silicon interposer-based hybrid voltage regulator system for VLSI devices Grant 7,952,194 - Nair , et al. May 31, 2	2011-05-31
Forming abrupt source drain metal gate transistors Grant 7,951,673 - Lindert , et al. May 31, 2	2011-05-31
Designs And Methods For Conductive Bumps App 20110084387 - Dubin; Valery M. ; et al.	2011-04-14
Copper die bumps with electromigration cap and plated solder Grant 7,919,859 - Zhong , et al. April 5, 2	2011-04-05
Forming self-aligned nano-electrodes Grant 7,755,082 - Dubin , et al. July 13, 2	2010-07-13
Forming Abrupt Source Drain Metal Gate Transistors App 20100151669 - Lindert; Nick ; et al.	2010-06-17
Method of forming abrupt source drain metal gate transistors Grant 7,704,833 - Lindert , et al. April 27, 2	2010-04-27
Transistor performance enhancement using engineered strains Grant 7,679,145 - He , et al. March 16, 2	2010-03-16
Methods of forming electromigration and thermal gradient based fuse structures Grant 7,662,674 - Maiz , et al. February 16, 2	2010-02-16
Selective Spacer Formation On Transistors Of Different Classes On The Same Device App 20090189193 - CURELLO; GIUSEPPE ; et al.	2009-07-30
Active region spacer for semiconductor devices and method to form the same Grant 7,560,780 - Curello , et al. July 14, 2	2009-07-14
Selective spacer formation on transistors of different classes on the same device Grant 7,541,239 - Curello , et al. June 2, 2	2009-06-02
Interconnect shunt used for current distribution and reliability redundancy Grant 7,524,754 - Bohr , et al. April 28, 2	2009-04-28
LOCOS isolation for fully-depleted SOI devices Grant 7,510,927 - Bohr , et al. March 31, 2	2009-03-31
Transistors with increased mobility in the channel zone and method of fabrication Grant 7,491,988 - Tolchinsky , et al. February 17, 2	2009-02-17
Microcircuit fabrication and interconnection Grant 7,470,620 - Dubin , et al. December 30, 2	2008-12-30
Copper die bumps with electromigration cap and plated solder App 20080230896 - Zhong; Ting ; et al.	2008-09-25
Strained silicon MOS device with box layer between the source and drain regions Grant 7,422,950 - Curello , et al. September 9, 2	2008-09-09
Designs and methods for conductive bumps App 20080213996 - Dubin; Valery M. ; et al.	2008-09-04
Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same Grant 7,414,298 - Ahmed , et al. August 19, 2	2008-08-19
Microcircuit Fabrication And Interconnection App 20080119016 - Dubin; Valery M. ; et al.	2008-05-22
Forming self-aligned nano-electrodes App 20080116439 - Dubin; Valery M. ; et al.	2008-05-22
Microcircuit fabrication and interconnection Grant 7,348,675 - Dubin , et al. March 25, 2	2008-03-25
Selective spacer formation on transistors of different classes on the same device App 20080003746 - Curello; Giuseppe ; et al.	2008-01-03
Forming self-aligned nano-electrodes Grant 7,312,155 - Dubin , et al. December 25, 2	2007-12-25
Copper-filled trench contact for transistor performance improvement App 20070273042 - Kuhn; Kelin J. ; et al.	2007-11-29
Designs and methods for conductive bumps Grant 7,276,801 - Dubin , et al. October 2, 2	2007-10-02
Isolation body for semiconductor devices and method to form the same App 20070132034 - Curello; Giuseppe ; et al.	2007-06-14
Strained silicon MOS device with box layer between the source and drain regions App 20070134859 - Curello; Giuseppe ; et al.	2007-06-14
Active region spacer for semiconductor devices and method to form the same App 20070132057 - Curello; Giuseppe ; et al.	2007-06-14
Interconnect shunt used for current distribution and reliability redundancy Grant 7,208,830 - Bohr , et al. April 24, 2	2007-04-24
Self aligned compact bipolar junction transistor layout and method of making same Grant 7,202,514 - Ahmed , et al. April 10, 2	2007-04-10
Methods of forming electromigration and thermal gradient based fuse structures App 20070069331 - Maiz; Jose A. ; et al.	2007-03-29
Damascene process for fabricating interconnect layers in an integrated circuit Grant 7,157,380 - Dubin , et al. January 2, 2	2007-01-02
Methods of forming electromigration and thermal gradient based fuse structures App 20060261437 - Maiz; Jose A. ; et al.	2006-11-23
Stepped tip junction with spacer layer Grant 7,112,859 - Ban , et al. September 26, 2	2006-09-26
Self-aligned contacts to gates Grant 7,109,102 - Bohr September 19, 2	2006-09-19
Concentration graded carbon doped oxide Grant 7,091,615 - Andideh , et al. August 15, 2	2006-08-15
Self-aligned contacts to gates Grant 7,091,610 - Bohr August 15, 2	2006-08-15
Self aligned compact bipolar junction transistor layout, and method of making same Grant 7,064,042 - Ahmed , et al. June 20, 2	2006-06-20
Bipolar junction transistor with improved extrinsic base region and method of fabrication App 20060113634 - Ahmed; Shahriar ; et al.	2006-06-01
Interconnect shunt used for current distribution and reliability redundancy App 20060097375 - Bohr; Mark ; et al.	2006-05-11
Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same Grant 7,015,085 - Ahmed , et al. March 21, 2	2006-03-21
Forming abrupt source drain metal gate transistors App 20060046399 - Lindert; Nick ; et al.	2006-03-02
Transistor performance enhancement using engineered strains App 20060043579 - He; Jun ; et al.	2006-03-02
Bipolar junction transistor with improved extrinsic base region and method of fabrication Grant 7,005,359 - Ahmed , et al. February 28, 2	2006-02-28
Interconnect shunt used for current distribution and reliability redundancy App 20060001178 - Bohr; Mark ; et al.	2006-01-05
Transistors with increased mobility in the channel zone and method of fabrication App 20050285212 - Tolchinsky, Peter G. ; et al.	2005-12-29
Stepped tip junction with spacer layer App 20050253192 - Ban, Ibrahim ; et al.	2005-11-17
Forming self-aligned nano-electrodes App 20050224778 - Dubin, Valery M. ; et al.	2005-10-13
Microcircuit fabrication and interconnection Grant 6,933,222 - Dubin , et al. August 23, 2	2005-08-23
Microcircuit fabrication and interconnection App 20050167755 - Dubin, Valery M. ; et al.	2005-08-04
Concentration graded carbon doped oxide App 20050161827 - Andideh, Ebrahim ; et al.	2005-07-28
Silicon on insulator (SOI) transistor and methods of fabrication Grant 6,919,238 - Bohr July 19, 2	2005-07-19
Damascene process for fabricating interconnect layers in an integrated circuit App 20050148190 - Dubin, Valery M. ; et al.	2005-07-07
Bipolar junction transistor with improved extrinsic base region and method of fabrication App 20050104160 - Ahmed, Shahriar ; et al.	2005-05-19
Concentration graded carbon doped oxide Grant 6,887,780 - Andideh , et al. May 3, 2	2005-05-03
Designs and methods for conductive bumps App 20050062169 - Dubin, Valery M. ; et al.	2005-03-24
Microcircuit fabrication and interconnection App 20040253805 - Dubin, Valery M. ; et al.	2004-12-16
Self-aligned contacts to gates App 20040229473 - Bohr, Mark	2004-11-18
N-p butting connections on SOI substrates Grant 6,762,464 - Webb , et al. July 13, 2	2004-07-13
Locos isolation for fully-depleted SOI devices App 20040124490 - Bohr, Mark ; et al.	2004-07-01
Self-aligned contacts to gates App 20040104419 - Bohr, Mark	2004-06-03
N-p butting connections on SOI substrates App 20040051144 - Webb, Clair ; et al.	2004-03-18
Super self-aligned collector device for mono-and hetero bipolar junction transistors Grant 6,703,685 - Ahmed , et al. March 9, 2	2004-03-09
Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same App 20040021206 - Ahmed, Shahriar ; et al.	2004-02-05
Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same App 20040021202 - Ahmed, Shahriar ; et al.	2004-02-05
Self-aligned contacts to gates Grant 6,686,247 - Bohr February 3, 2	2004-02-03
Silicon on isulator (SOI) transistor and methods of fabrication App 20040016969 - Bohr, Mark	2004-01-29
Silicon on insulator (SOI) transistor and methods of fabrication App 20040018672 - Bohr, Mark	2004-01-29
Self aligned compact bipolar junction transistor layout and method of making same App 20030219939 - Ahmed, Shahriar ; et al.	2003-11-27
Patterning tighter and looser pitch geometries App 20030207584 - Sivakumar, Swaminathan ; et al.	2003-11-06
Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same App 20030107106 - Ahmed, Shahriar ; et al.	2003-06-12
Self Aligned Compact Bipolar Junction Transistor Layout, And Method Of Making Same App 20030109108 - Ahmed, Shahriar ; et al.	2003-06-12
Silicon interposer-based hybrid voltage regulator system for VLSI devices App 20030081389 - Nair, Raj ; et al.	2003-05-01
Concentration graded carbon doped oxide App 20030042605 - Andideh, Ebrahim ; et al.	2003-03-06
Integrated Circuit Processing With Improved Gate Electrode Fabrication App 20010039083 - BOHR, MARK	2001-11-08

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