Boggs; Darrell D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Boggs; Darrell D..The latest application filed is for "memory type which is cacheable yet inaccessible by speculative instructions".

Company Profile

2.35.28

Boggs; Darrell D. - Hillsboro OR
Boggs; Darrell D. - Aloha OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory type which is cacheable yet inaccessible by speculative instructions Grant 10,642,744 - Boggs , et al.	2020-05-05
Memory Type Which Is Cacheable Yet Inaccessible By Speculative Instructions App 20190004961 - BOGGS; Darrell D. ; et al.	2019-01-03
Lazy runahead operation for a microprocessor Grant 9,891,972 - Ekman , et al. February 13, 2	2018-02-13
Queued instruction re-dispatch after runahead Grant 9,823,931 - Rozas , et al. November 21, 2	2017-11-21
Managing potentially invalid results during runahead Grant 9,740,553 - Holmer , et al. August 22, 2	2017-08-22
Lazy Runahead Operation For A Microprocessor App 20170199778 - Ekman; Magnus ; et al.	2017-07-13
Lazy runahead operation for a microprocessor Grant 9,632,976 - Rozas , et al. April 25, 2	2017-04-25
Dynamic configuration of processing pipeline based on determined type of fetched instruction Grant 9,563,432 - Segelken , et al. February 7, 2	2017-02-07
Dynamic Configuration Of Processing Pipeline Based On Determined Type Of Fetched Instruction App 20140317382 - Segelken; Ross ; et al.	2014-10-23
Queued Instruction Re-dispatch After Runahead App 20140189313 - Rozas; Guillermo J. ; et al.	2014-07-03
Instruction Categorization For Runahead Operation App 20140164738 - Ekman; Magnus ; et al.	2014-06-12
Lazy Runahead Operation For A Microprocessor App 20140164736 - Rozas; Guillermo J. ; et al.	2014-06-12
Managing Potentially Invalid Results During Runahead App 20140136891 - Holmer; Bruce ; et al.	2014-05-15
Method and Apparatus for Assigning Thread Priority in a Processor or the Like App 20110239221 - Burns; David W. ; et al.	2011-09-29
Method and apparatus for assigning thread priority in a processor or the like Grant 7,987,346 - Burns , et al. July 26, 2	2011-07-26
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like App 20110113222 - BURNS; David W. ; et al.	2011-05-12
Method and apparatus for assigning thread priority in a processor or the like Grant 7,877,583 - Burns , et al. January 25, 2	2011-01-25
Programmable event driven yield mechanism which may activate service threads Grant 7,849,465 - Zou , et al. December 7, 2	2010-12-07
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like App 20090070562 - BURNS; David W. ; et al.	2009-03-12
Method and apparatus for assigning thread priority in a processor or the like Grant 7,454,600 - Burns , et al. November 18, 2	2008-11-18
Bit field selection instruction App 20070124631 - Boggs; Darrell D. ; et al.	2007-05-31
Multi-threading techniques for a processor utilizing a replay queue Grant 7,219,349 - Merchant , et al. May 15, 2	2007-05-15
Microprocessor with customer code store Grant 7,216,220 - Brown , et al. May 8, 2	2007-05-08
Instruction packer for digital signal processor App 20070083736 - Baktha; Aravindh ; et al.	2007-04-12
Processor with a replay system that includes a replay queue for improved throughput Grant 7,200,737 - Merchant , et al. April 3, 2	2007-04-03
Prediction of load-store dependencies in a processing agent Grant 7,181,598 - Jourdan , et al. February 20, 2	2007-02-20
Programmable event driven yield mechanism which may activate service threads App 20060294347 - Zou; Xiang ; et al.	2006-12-28
Rounding correction for add-shift-round instruction with dual-use source operand for DSP App 20060218381 - Fogg; Chad E. ; et al.	2006-09-28
Add-shift-round instruction with dual-use source operand for DSP App 20060218380 - Boggs; Darrell D. ; et al.	2006-09-28
Instruction with dual-use source providing both an operand value and a control value App 20060218377 - Boggs; Darrell D. ; et al.	2006-09-28
Interface to a memory system for a processor having a replay system Grant 7,089,409 - Merchant , et al. August 8, 2	2006-08-08
Method and apparatus for managing resources in a multithreaded processor Grant 7,051,329 - Boggs , et al. May 23, 2	2006-05-23
Clip instruction for processor App 20060095714 - Boggs; Darrell D. ; et al.	2006-05-04
Clip-and-pack instruction for processor App 20060095713 - Boggs; Darrell D. ; et al.	2006-05-04
Determining whether thread fetch operation will be blocked due to processing of another thread Grant 7,010,669 - Burns , et al. March 7, 2	2006-03-07
Scalable matrix register file App 20060036801 - Jones; Christpher S. ; et al.	2006-02-16
Microprocessor with branch target determination in decoded microinstruction code sequence App 20060015708 - Boggs; Darrell D. ; et al.	2006-01-19
Microprocessor with customer code store App 20060015707 - Brown; Gary L. ; et al.	2006-01-19
Breaking replay dependency loops in a processor using a rescheduled replay queue Grant 6,981,129 - Boggs , et al. December 27, 2	2005-12-27
Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter Grant 6,877,086 - Boggs , et al. April 5, 2	2005-04-05
Branch ordering buffer Grant 6,799,268 - Boggs , et al. September 28, 2	2004-09-28
Processor having a RAT state history recovery mechanism App 20040177239 - Clift, David W. ; et al.	2004-09-09
Control word register renaming Grant 6,779,103 - Alexander, III , et al. August 17, 2	2004-08-17
Interface to a memory system for a processor having a replay system App 20040083351 - Merchant, Amit A. ; et al.	2004-04-29
Method and apparatus for resolving instruction starvation in a processor or the like App 20040078794 - Burns, David W. ; et al.	2004-04-22
Interface to a memory system for a processor having a replay system Grant 6,665,792 - Merchant , et al. December 16, 2	2003-12-16
Prediction of load-store dependencies in a processing agent App 20030217251 - Jourdan, Stephan J. ; et al.	2003-11-20
Determination of approaching instruction starvation of threads based on a plurality of conditions Grant 6,651,158 - Burns , et al. November 18, 2	2003-11-18
Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer Grant 6,633,970 - Clift , et al. October 14, 2	2003-10-14
Method and system for an INUSE field resource management scheme App 20030023816 - Kyker, Alan B. ; et al.	2003-01-30
Method and apparatus for resolving instruction starvation in a processor or the like App 20020199089 - Burns, David W. ; et al.	2002-12-26
Method and apparatus for assigning thread priority in a processor or the like App 20020199088 - Burns, David W. ; et al.	2002-12-26
Method and system for an INUSE field resource management scheme Grant 6,467,027 - Kyker , et al. October 15, 2	2002-10-15
Multi-threading for a processor utilizing a replay queue Grant 6,385,715 - Merchant , et al. May 7, 2	2002-05-07
Computer processor with a replay system Grant 6,163,838 - Merchant , et al. December 19, 2	2000-12-19
Computer processor with a replay system having a plurality of checkers Grant 6,094,717 - Merchant , et al. July 25, 2	2000-07-25
Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool Grant 6,026,477 - Kyker , et al. February 15, 2	2000-02-15
Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor Grant 5,687,338 - Boggs , et al. November 11, 1	1997-11-11
Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto Grant 5,625,788 - Boggs , et al. April 29, 1	1997-04-29
Decoding circuit and method providing immediate data for a micro-operation issued from a decoder Grant 5,581,717 - Boggs , et al. December 3, 1	1996-12-03
Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation Grant 5,559,974 - Boggs , et al. September 24, 1	1996-09-24
Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor Grant 5,537,560 - Boggs , et al. July 16, 1	1996-07-16
Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system Grant 5,463,745 - Vidwans , et al. October 31, 1	1995-10-31

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