Boersma; Maarten J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Boersma; Maarten J..The latest application filed is for "instruction handling for accumulation of register results in a microprocessor".

Company Profile

25.51.48

Boersma; Maarten J. - Holzgerlingen DE
BOERSMA; MAARTEN J. - BOEBLINGEN DE
Boersma; Maarten J. - Holzerlingen N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instruction Handling For Accumulation Of Register Results In A Microprocessor App 20220050682 - Thompto; Brian W. ; et al.	2022-02-17
On-the-fly Adjustment Of Issue-write Back Latency To Avoid Write Back Collisions Using A Result Buffer App 20220035637 - Barrick; Brian D. ; et al.	2022-02-03
Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads Grant 11,182,167 - Ingimundarson , et al. November 23, 2	2021-11-23
Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry Grant 11,157,276 - Battle , et al. October 26, 2	2021-10-26
Dynamic fusion based on operand size Grant 11,157,280 - Boersma , et al. October 26, 2	2021-10-26
Instruction handling for accumulation of register results in a microprocessor Grant 11,132,198 - Thompto , et al. September 28, 2	2021-09-28
Banked slice-target register file for wide dataflow execution in a microprocessor Grant 11,093,246 - Boersma , et al. August 17, 2	2021-08-17
Low latency execution of floating-point record form instructions Grant 10,996,953 - Barrick , et al. May 4, 2	2021-05-04
Banked Slice-target Register File For Wide Dataflow Execution In A Microprocessor App 20210072991 - Boersma; Maarten J. ; et al.	2021-03-11
Thread-based Organization Of Slice Target Register File Entry In A Microprocessor App 20210072993 - Battle; Steven J. ; et al.	2021-03-11
Instruction Handling For Accumulation Of Register Results In A Microprocessor App 20210064365 - Thompto; Brian W. ; et al.	2021-03-04
Method to execute successive dependent instructions from an instruction stream in a processor Grant 10,831,496 - Boersma , et al. November 10, 2	2020-11-10
Method To Determine The Oldest Instruction In An Instruction Queue Of A Processor With Multiple Instruction Threads App 20200293328 - Ingimundarson; Arni ; et al.	2020-09-17
Arithmetic logic unit for single-cycle fusion operations Grant 10,768,897 - Boersma , et al. Sep	2020-09-08
Method To Execute Successive Dependent Instructions From An Instruction Stream In A Processor App 20200278868 - Boersma; Maarten J. ; et al.	2020-09-03
Low latency execution of floating-point record form instructions Grant 10,678,547 - Barrick , et al.	2020-06-09
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core Grant 10,671,399 - Boersma , et al.	2020-06-02
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core Grant 10,671,398 - Boersma , et al.	2020-06-02
Low latency execution of floating-point record form instructions Grant 10,592,246 - Barrick , et al.	2020-03-17
Arithmetic logic unit for single-cycle fusion operations Grant 10,545,727 - Boersma , et al. Ja	2020-01-28
Arithmetic Logic Unit For Single-cycle Fusion Operations App 20200019376 - Boersma; Maarten J. ; et al.	2020-01-16
Low Latency Execution Of Floating-point Record Form Instructions App 20190391810 - Barrick; Brian J.D. ; et al.	2019-12-26
Cracked execution of move-to-FPSCR instructions Grant 10,360,036 - Barrick , et al.	2019-07-23
Arithmetic Logic Unit For Single-cycle Fusion Operations App 20190212984 - Boersma; Maarten J. ; et al.	2019-07-11
Dynamic Fusion Based On Operand Size App 20190179639 - Boersma; Maarten J. ; et al.	2019-06-13
ECC scrubbing method in a multi-slice microprocessor Grant 10,223,196 - Barrick , et al.	2019-03-05
Low-overhead, Low-latency Operand Dependency Tracking For Instructions Operating On Register Pairs In A Processor Core App 20190042268 - Boersma; Maarten J. ; et al.	2019-02-07
Low-overhead, Low-latency Operand Dependency Tracking For Instructions Operating On Register Pairs In A Processor Core App 20190042267 - Boersma; Maarten J. ; et al.	2019-02-07
Low Latency Execution Of Floating-point Record Form Instructions App 20190018685 - Barrick; Brian J.D. ; et al.	2019-01-17
Low Latency Execution Of Floating-point Record Form Instructions App 20190018684 - Barrick; Brian J.D. ; et al.	2019-01-17
Cracked Execution Of Move-to-fpscr Instructions App 20190018678 - Barrick; Brian J.D. ; et al.	2019-01-17
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Grant 10,169,046 - Boersma , et al. J	2019-01-01
Out-of-order Processor That Avoids Deadlock In Processing Queues By Designating A Most Favored Instruction App 20180121205 - Boersma; Maarten J. ; et al.	2018-05-03
Ecc Scrubbing Method In A Multi-slice Microprocessor App 20180095820 - Barrick; Brian D. ; et al.	2018-04-05
Techniques For Implementing Store Instructions In A Multi-slice Processor Architecture App 20170364356 - AYUB; SALMA ; et al.	2017-12-21
ECC scrubbing in a multi-slice microprocessor Grant 9,846,614 - Barrick , et al. December 19, 2	2017-12-19
Ecc Scrubbing In A Multi-slice Microprocessor App 20170351568 - BARRICK; Brian D. ; et al.	2017-12-07
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Grant 9,798,549 - Boersma , et al. October 24, 2	2017-10-24
Register files for storing data operated on by instructions of multiple widths Grant 9,760,375 - Boersma , et al. September 12, 2	2017-09-12
Splitable and scalable normalizer for vector data Grant 9,753,690 - Boersma , et al. September 5, 2	2017-09-05
Register files for storing data operated on by instructions of multiple widths Grant 9,740,486 - Boersma , et al. August 22, 2	2017-08-22
Pipeline depth exploration in a register transfer level design description of an electronic circuit Grant 9,684,749 - Boersma , et al. June 20, 2	2017-06-20
Active power dissipation detection based on erroneus clock gating equations Grant 9,495,490 - Abernathy , et al. November 15, 2	2016-11-15
Splitable And Scalable Normalizer For Vector Data App 20160253152 - Boersma; Maarten J. ; et al.	2016-09-01
Splitable and scalable normalizer for vector data Grant 9,361,267 - Boersma , et al. June 7, 2	2016-06-07
Splitable and scalable normalizer for vector data Grant 9,361,268 - Boersma , et al. June 7, 2	2016-06-07
Fast normalization in a mixed precision floating-point unit Grant 9,286,031 - Boersma , et al. March 15, 2	2016-03-15
Register Files For Storing Data Operated On By Instructions Of Multiple Widths App 20160070574 - Boersma; Maarten J. ; et al.	2016-03-10
Register Files For Storing Data Operated On By Instructions Of Multiple Widths App 20160070571 - Boersma; Maarten J. ; et al.	2016-03-10
Fast normalization in a mixed precision floating-point unit Grant 9,280,316 - Boersma , et al. March 8, 2	2016-03-08
Verification of a vector execution unit design Grant 9,274,791 - Boersma , et al. March 1, 2	2016-03-01
Verification of a vector execution unit design Grant 9,268,563 - Boersma , et al. February 23, 2	2016-02-23
Fused multiply-adder with booth-encoding Grant 9,256,397 - Boersma , et al. February 9, 2	2016-02-09
Mechanism to speed-up multithreaded execution by register file write port reallocation Grant 9,207,995 - Boersma , et al. December 8, 2	2015-12-08
Apparatus and method for calculating an SHA-2 hash function in a general purpose processor Grant 9,164,725 - Boersma , et al. October 20, 2	2015-10-20
Fused multiply-adder with booth-encoding Grant 9,122,517 - Boersma , et al. September 1, 2	2015-09-01
Pipeline Depth Exploration In A Register Transfer Level Design Description Of An Electronic Circuit App 20150234968 - Boersma; Maarten J. ; et al.	2015-08-20
Fast Normalization In A Mixed Precision Floating-point Unit App 20150149521 - Boersma; Maarten J. ; et al.	2015-05-28
Fast Normalization In A Mixed Precision Floating-point Unit App 20150149522 - Boersma; Maarten J. ; et al.	2015-05-28
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Grant 8,977,835 - Boersma , et al. March 10, 2	2015-03-10
Splitable And Scalable Normalizer For Vector Data App 20150067299 - Boersma; Maarten J. ; et al.	2015-03-05
Splitable And Scalable Normalizer For Vector Data App 20150067298 - Boersma; Maarten J. ; et al.	2015-03-05
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Grant 8,949,575 - Boersma , et al. February 3, 2	2015-02-03
Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product Grant 8,903,882 - Boersma , et al. December 2, 2	2014-12-02
Verification Of A Vector Execution Unit Design App 20140156969 - BOERSMA; MAARTEN J. ; et al.	2014-06-05
Verification Of A Vector Execution Unit Design App 20140136815 - Boersma; Maarten J. ; et al.	2014-05-15
Fused Multiply-Adder with Booth-Encoding App 20140095568 - BOERSMA; MAARTEN J. ; et al.	2014-04-03
Reducing Issue-to-issue Latency By Reversing Processing Order In Half-pumped Simd Execution Units App 20140075153 - Boersma; Maarten J. ; et al.	2014-03-13
Active Power Dissipation Detection Based On Erronous Clock Gating Equations App 20140019780 - Abernathy; Christopher M. ; et al.	2014-01-16
Fused Multiply-Adder with Booth-Encoding App 20130332501 - Boersma; Maarten J. ; et al.	2013-12-12
Zero indication forwarding for floating point unit power reduction Grant 8,578,196 - Barowski , et al. November 5, 2	2013-11-05
Reducing Issue-to-issue Latency By Reversing Processing Order In Half-pumped Simd Execution Units App 20130159666 - Boersma; Maarten J. ; et al.	2013-06-20
Fast floating point compare with slower backup for corner cases Grant 8,407,275 - Boersma , et al. March 26, 2	2013-03-26
Efficient forcing of corner cases in a floating point rounder Grant 8,352,531 - Boersma , et al. January 8, 2	2013-01-08
Zero Indication Forwarding for Floating Point Unit Power Reduction App 20120284548 - Barowski; Harry S. ; et al.	2012-11-08
Supporting multiple formats in a floating point processor Grant 8,291,003 - Boersma , et al. October 16, 2	2012-10-16
Zero indication forwarding for floating point unit power reduction Grant 8,255,726 - Barowski , et al. August 28, 2	2012-08-28
Normalizer shift prediction for log estimate instructions Grant 8,244,783 - Boersma , et al. August 14, 2	2012-08-14
Method And Data Processing Unit For Calculating At Least One Multiply-sum Of Two Carry-less Multiplications Of Two Input Operands, Data Processing Program And Computer Program Product App 20120150933 - Boersma; Maarten J. ; et al.	2012-06-14
Apparatus And Method For Calculating An Sha-2 Hash Function In A General Purpose Processor App 20120128149 - Boersma; Maarten J. ; et al.	2012-05-24
Mechanism To Speed-up Multithreaded Execution By Register File Write Port Reallocation App 20120110271 - Boersma; Maarten J. ; et al.	2012-05-03
Fast Floating Point Compare With Slower Backup For Corner Cases App 20100100713 - Boersma; Maarten J. ; et al.	2010-04-22
Supporting Multiple Formats In A Floating Point Processor App 20100063987 - Boersma; Maarten J. ; et al.	2010-03-11
Normalizer Shift Prediction For Log Estimate Instructions App 20100063985 - Boersma; Maarten J. ; et al.	2010-03-11
Efficient Forcing Of Corner Cases In A Floating Point Rounder App 20100023573 - Boersma; Maarten J. ; et al.	2010-01-28
Zero Indication Forwarding For Floating Point Unit Power Reduction App 20100017635 - BAROWSKI; HARRY S. ; et al.	2010-01-21

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