Boda; Veerabhadra Rao
Patent Applications and Registrations
Patent applications and USPTO patent grants for Boda; Veerabhadra Rao.The latest application filed is for "memory with improved write time and reduced write power".
- Boda; Veerabhadra Rao - Bangalore IN
- Boda; Veerabhadra Rao - East Godavari IN
| Patent | Date |
|---|---|
| Systems and methods for control signal latching in memories Grant 11,152,921 - Boda , et al. October 19, 2 | 2021-10-19 |
| SRAM write yield enhancement with pull-up strength modulation Grant 10,811,086 - Mohanty , et al. October 20, 2 | 2020-10-20 |
| Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories Grant 9,928,889 - Narasimhan , et al. March 27, 2 | 2018-03-27 |
| Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power Grant 9,865,316 - Gupta , et al. January 9, 2 | 2018-01-09 |
| Memory With Improved Write Time And Reduced Write Power App 20170213587 - Gupta; Sharad Kumar ; et al. | 2017-07-27 |
| Pulse latch reset tracking at high differential voltage Grant 9,607,674 - Narasimhan , et al. March 28, 2 | 2017-03-28 |
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