| Patent | Date |
|---|
Texture state cache
Grant 9,811,875 - Goodman , et al. November 7, 2 | 2017-11-07 |
Hint values for use with an operand cache
Grant 9,652,233 - Potter , et al. May 16, 2 | 2017-05-16 |
Instruction source specification
Grant 9,632,785 - Blomgren , et al. April 25, 2 | 2017-04-25 |
Result bypass cache
Grant 9,600,288 - Potter , et al. March 21, 2 | 2017-03-21 |
Clock routing techniques
Grant 9,594,395 - Havlir , et al. March 14, 2 | 2017-03-14 |
Instruction Source Specification
App 20160350113 - Blomgren; James S. ; et al. | 2016-12-01 |
Multi-threaded GPU pipeline
Grant 9,508,112 - Havlir , et al. November 29, 2 | 2016-11-29 |
Intelligent caching for an operand cache
Grant 9,459,869 - Olson , et al. October 4, 2 | 2016-10-04 |
Instruction source specification
Grant 9,442,730 - Blomgren , et al. September 13, 2 | 2016-09-13 |
Extended multiply
Grant 9,417,843 - Blomgren , et al. August 16, 2 | 2016-08-16 |
Operand cache design
Grant 9,378,146 - Blomgren , et al. June 28, 2 | 2016-06-28 |
Interpolation implementation
Grant 9,292,285 - Blomgren March 22, 2 | 2016-03-22 |
Texture State Cache
App 20160071232 - Goodman; Benjiman L. ; et al. | 2016-03-10 |
Type conversion using floating-point unit
Grant 9,264,066 - Blomgren , et al. February 16, 2 | 2016-02-16 |
Clock Routing Techniques
App 20150205324 - Havlir; Andrew M. ; et al. | 2015-07-23 |
Operand Cache Design
App 20150058573 - Blomgren; James S. ; et al. | 2015-02-26 |
Intelligent Caching For An Operand Cache
App 20150058572 - Olson; Timothy A. ; et al. | 2015-02-26 |
Extended Multiply
App 20150058389 - Blomgren; James S. ; et al. | 2015-02-26 |
Hint Values For Use With An Operand Cache
App 20150058571 - Potter; Terence M. ; et al. | 2015-02-26 |
Interpolation Implementation
App 20150052335 - Blomgren; James S. | 2015-02-19 |
Type Conversion Using Floating-point Unit
App 20150039661 - Blomgren; James S. ; et al. | 2015-02-05 |
Instruction Source Specification
App 20150039867 - Blomgren; James S. ; et al. | 2015-02-05 |
Multi-threaded Gpu Pipeline
App 20150035841 - Havlir; Andrew M. ; et al. | 2015-02-05 |
Reduced voltage swing clock distribution
Grant 8,482,333 - Runas , et al. July 9, 2 | 2013-07-09 |
Reduced Voltage Swing Clock Distribution
App 20130093485 - Runas; Michael E. ; et al. | 2013-04-18 |
Expansion syntax
Grant 7,299,461 - Boehm , et al. November 20, 2 | 2007-11-20 |
Physical realization of dynamic logic using parameterized tile partitioning
Grant 7,219,326 - Reed , et al. May 15, 2 | 2007-05-15 |
Null value propagation for FAST14 logic
Grant 7,053,664 - Potter , et al. May 30, 2 | 2006-05-30 |
Software modeling of logic signals capable of holding more than two values
Grant 7,031,897 - Blomgren , et al. April 18, 2 | 2006-04-18 |
Static storage element for dynamic logic
Grant 6,956,406 - Seningen , et al. October 18, 2 | 2005-10-18 |
Method and apparatus for a 1 of N signal
Grant 6,911,846 - Blomgren , et al. June 28, 2 | 2005-06-28 |
Rearranging data between vector and matrix forms in a SIMD matrix processor
Grant 6,898,691 - Blomgren , et al. May 24, 2 | 2005-05-24 |
Physical realization of dynamic logic using parameterized tile partitioning
App 20050060128 - Reed, Jeffrey B. ; et al. | 2005-03-17 |
Expansion syntax
App 20040139423 - Boehm, Fritz A. ; et al. | 2004-07-15 |
Dynamic logic scan gate method and apparatus
Grant 6,745,357 - Chrudimsky , et al. June 1, 2 | 2004-06-01 |
Static transmission of FAST14 logic 1-of-N signals
Grant 6,714,045 - Potter , et al. March 30, 2 | 2004-03-30 |
Null value propagation for FAST14 logic
App 20040006753 - Potter, Terence M. ; et al. | 2004-01-08 |
Method and apparatus for pre-branch instruction
Grant 6,622,240 - Olson , et al. September 16, 2 | 2003-09-16 |
Multiple-state simulation for non-binary logic
Grant 6,604,065 - Blomgren , et al. August 5, 2 | 2003-08-05 |
Static storage element for dynamic logic
App 20030110404 - Seningen, Michael R. ; et al. | 2003-06-12 |
Static transmisstion of FAST14 logic 1-of-N signals
App 20030042935 - Potter, Terence M. ; et al. | 2003-03-06 |
Rearranging data between vector and matrix forms in a SIMD matrix processor
App 20020198911 - Blomgren, James S. ; et al. | 2002-12-26 |
Method and apparatus for a late pipeline enhanced floating point unit
Grant 6,460,134 - Blomgren , et al. October 1, 2 | 2002-10-01 |
Method For Calculating Dynamic Logic Block Propagation Delay Targets Using Time Borrowing
App 20020067187 - Vijayan, Gopal ; et al. | 2002-06-06 |
Method and apparatus that enforces a regional memory model in hierarchical memory systems
Grant 6,370,632 - Kikuta , et al. April 9, 2 | 2002-04-09 |
Method and apparatus for handling partial register accesses
Grant 6,334,183 - Blomgren , et al. December 25, 2 | 2001-12-25 |
Dynamic logic scan gate method and apparatus
App 20010039635 - Chrudimsky, David W. ; et al. | 2001-11-08 |
Method and apparatus for dynamic partitionable saturating adder/subtractor
Grant 6,301,600 - Petro , et al. October 9, 2 | 2001-10-09 |
Method and apparatus for generating clock signals
Grant 6,288,589 - Potter , et al. September 11, 2 | 2001-09-11 |
1-of-4 multiplier
Grant 6,275,841 - Potter , et al. August 14, 2 | 2001-08-14 |
Method and apparatus for an enhanced floating point unit with graphics and integer capabilities
Grant 6,275,838 - Blomgren , et al. August 14, 2 | 2001-08-14 |
Method and apparatus for logic synchronization
Grant 6,268,746 - Potter , et al. July 31, 2 | 2001-07-31 |
Method and apparatus for TLB memory ordering
Grant 6,260,131 - Kikuta , et al. July 10, 2 | 2001-07-10 |
Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock
Grant 6,233,707 - Potter , et al. May 15, 2 | 2001-05-15 |
Method and apparatus for routing 1 of 4 signals
Grant 6,211,456 - Seningen , et al. April 3, 2 | 2001-04-03 |
Method and apparatus for two-stage address generation
Grant 6,209,076 - Blomgren March 27, 2 | 2001-03-27 |
Method and apparatus for a N-nary logic circuit using capacitance isolation
Grant 6,124,735 - Blomgren , et al. September 26, 2 | 2000-09-26 |
Method and apparatus for a logic circuit with constant power consumption
Grant 6,107,835 - Blomgren , et al. August 22, 2 | 2000-08-22 |
Method and apparatus for a N-nary logic circuit using 1 of N signals
Grant 6,069,497 - Blomgren , et al. May 30, 2 | 2000-05-30 |
Method and apparatus for a N-nary logic circuit using 1 of 4 signals
Grant 6,066,965 - Blomgren , et al. May 23, 2 | 2000-05-23 |
Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier
Grant 5,935,198 - Blomgren August 10, 1 | 1999-08-10 |
Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
Grant 5,884,057 - Blomgren , et al. March 16, 1 | 1999-03-16 |
Debug and video queue for multi-processor chip
Grant 5,848,264 - Baird , et al. December 8, 1 | 1998-12-08 |
Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield
Grant 5,828,578 - Blomgren October 27, 1 | 1998-10-27 |
Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
Grant 5,826,074 - Blomgren October 20, 1 | 1998-10-20 |
Early instruction-length pre-decode of variable-length instructions in a superscalar processor
Grant 5,809,272 - Thusoo , et al. September 15, 1 | 1998-09-15 |
Mixed-modulo address generation using shadow segment registers
Grant 5,790,443 - Shen , et al. August 4, 1 | 1998-08-04 |
Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
Grant 5,781,457 - Cohen , et al. July 14, 1 | 1998-07-14 |
Dual-instruction-set architecture CPU with hidden software emulation mode
Grant 5,781,750 - Blomgren , et al. July 14, 1 | 1998-07-14 |
Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
Grant 5,745,913 - Pattin , et al. April 28, 1 | 1998-04-28 |
Self-testing multi-processor die with internal compare points
Grant 5,732,209 - Vigil , et al. March 24, 1 | 1998-03-24 |
Stack push/pop tracking and pairing in a pipelined processor
Grant 5,687,336 - Shen , et al. November 11, 1 | 1997-11-11 |
Shared floating-point registers and register port-pairing in a dual-architecture CPU
Grant 5,685,009 - Blomgren , et al. November 4, 1 | 1997-11-04 |
Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
Grant 5,664,159 - Richter , et al. September 2, 1 | 1997-09-02 |
Translator having segment bounds encoding for storage in a TLB
Grant 5,652,872 - Richter , et al. July 29, 1 | 1997-07-29 |
Splitting a floating-point stack-exchange instruction for merging into surrounding instructions by operand translation
Grant 5,634,118 - Blomgren May 27, 1 | 1997-05-27 |
Inexact leading-one/leading-zero prediction integrated with a floating-point adder
Grant 5,633,819 - Brashears , et al. May 27, 1 | 1997-05-27 |
Block-based branch prediction using a target finder array storing target sub-addresses
Grant 5,608,886 - Blomgren , et al. March 4, 1 | 1997-03-04 |
Dual-architecture super-scalar pipeline
Grant 5,598,546 - Blomgren January 28, 1 | 1997-01-28 |
Program watchpoint checking using paging with sub-page validity
Grant 5,598,553 - Richter , et al. January 28, 1 | 1997-01-28 |
Master-slave cache system for instruction and data cache memories
Grant 5,551,001 - Cohen , et al. August 27, 1 | 1996-08-27 |
Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
Grant 5,542,059 - Blomgren | 1996-07-30 |
Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities
Grant 5,542,109 - Blomgren , et al. July 30, 1 | 1996-07-30 |
Reduced-modulus address generation using sign-extension and correction
Grant 5,511,017 - Cohen , et al. April 23, 1 | 1996-04-23 |
Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
Grant 5,481,684 - Richter , et al. January 2, 1 | 1996-01-02 |
Bi-planar multi-chip module
Grant 5,477,082 - Buckley, III , et al. December 19, 1 | 1995-12-19 |
Microprocessor with operation capture facility
Grant 5,455,909 - Blomgren , et al. October 3, 1 | 1995-10-03 |
Emulation of segment bounds checking using paging with sub-page validity
Grant 5,440,710 - Richter , et al. August 8, 1 | 1995-08-08 |
Processor system with dual clock
Grant 5,325,516 - Blomgren , et al. June 28, 1 | 1994-06-28 |
System for detecting boundary cross-over of instruction memory space using reduced number of address bits
Grant 5,313,606 - Luong , et al. May 17, 1 | 1994-05-17 |
Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction
Grant 5,276,825 - Blomgren , et al. January 4, 1 | 1994-01-04 |
Microprocessor with OEM mode for power management with input/output intiated selection of special address space
Grant 5,274,791 - Bracking , et al. December 28, 1 | 1993-12-28 |
| 