Blodget; Brandon J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Blodget; Brandon J..The latest application filed is for "reconfiguration of a programmable logic device using internal control".

Company Profile

0.20.2

Blodget; Brandon J. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configuration of a large-scale reconfigurable computing arrangement using a virtual file system interface Grant 8,271,557 - Lysaght , et al. September 18, 2	2012-09-18
Debugging using a virtual file system interface Grant 7,890,916 - Donlin , et al. February 15, 2	2011-02-15
Bootable integrated circuit device for readback encoding of configuration data Grant 7,689,726 - Sundararajan , et al. March 30, 2	2010-03-30
Enhancing relocatability of partial configuration bitstreams Grant 7,673,271 - Becker , et al. March 2, 2	2010-03-02
Modular partial reconfiguration Grant 7,640,526 - Blodget , et al. December 29, 2	2009-12-29
Validating partial reconfiguration of an integrated circuit Grant 7,541,833 - Neuendorffer , et al. June 2, 2	2009-06-02
Method and apparatus for accessing internal registers of hardware blocks in a programmable logic device Grant 7,525,343 - Neuendorffer , et al. April 28, 2	2009-04-28
Concealed, non-intrusive watermarks for configuration bitstreams Grant 7,519,823 - Schumacher , et al. April 14, 2	2009-04-14
Virtual file system interface to configuration data of a PLD Grant 7,480,789 - Donlin , et al. January 20, 2	2009-01-20
Method and system for identifying essential configuration bits Grant 7,406,673 - Patterson , et al. July 29, 2	2008-07-29
Method and system for generating a bitstream view of a design Grant 7,343,578 - Patterson , et al. March 11, 2	2008-03-11
Programmably configurable logic-based macro Grant 7,337,422 - Becker , et al. February 26, 2	2008-02-26
Bootable programmable logic device for internal decoding of encoded configuration data Grant 7,328,335 - Sundararajan , et al. February 5, 2	2008-02-05
Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA Grant 7,249,010 - Sundararajan , et al. July 24, 2	2007-07-24
Reconfiguration of a programmable logic device using internal control Grant 7,227,378 - Blodget , et al. June 5, 2	2007-06-05
Reconfigurable multi-stage crossbar Grant 7,149,996 - Lysaght , et al. December 12, 2	2006-12-12
Reconfiguration of a programmable logic device using internal control App 20050193358 - Blodget, Brandon J. ; et al.	2005-09-01
Method and system for device-level simulation of a circuit design for a programmable logic device Grant 6,922,665 - Guccione , et al. July 26, 2	2005-07-26
Reconfiguration of a programmable logic device using internal control Grant 6,920,627 - Blodget , et al. July 19, 2	2005-07-19
Controller arrangement for partial reconfiguration of a programmable logic device Grant 6,810,514 - Alfke , et al. October 26, 2	2004-10-26
Reconfiguration of a programmable logic device using internal control App 20040117755 - Blodget, Brandon J. ; et al.	2004-06-17
Method and apparatus for pre-routing dynamic run-time reconfigurable logic cores Grant 6,510,546 - Blodget January 21, 2	2003-01-21

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