Block; Stefan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Block; Stefan.The latest application filed is for "edge cell signal line antenna diodes".
- Block; Stefan - Munich DE
- Block; Stefan - City of Munich DE
- Block; Stefan - Munchen DE
| Patent | Date |
|---|---|
| Edge cell signal line antenna diodes Grant 11,450,753 - Block , et al. September 20, 2 | 2022-09-20 |
| Edge Cell Signal Line Antenna Diodes App 20200357897 - Block; Stefan ; et al. | 2020-11-12 |
| Simplified bias scheme for digital designs Grant 10,505,545 - Block , et al. Dec | 2019-12-10 |
| Placing and routing method for implementing back bias in FDSOI Grant 10,114,919 - Preuthen , et al. October 30, 2 | 2018-10-30 |
| Reducing antenna effects in SOI devices Grant 9,773,811 - Lorenz , et al. September 26, 2 | 2017-09-26 |
| Reducing Antenna Effects In Soi Devices App 20170243894 - Lorenz; Ingolf ; et al. | 2017-08-24 |
| Placing And Routing Method For Implementing Back Bias In Fdsoi App 20170235865 - Preuthen; Herbert Johannes ; et al. | 2017-08-17 |
| Memory Cell, Memory Device Including A Plurality Of Memory Cells And Method Including Read And Write Operations At A Memory Cell App 20160284392 - Block; Stefan ; et al. | 2016-09-29 |
| Clock tree insertion delay independent interface Grant 8,564,337 - Block , et al. October 22, 2 | 2013-10-22 |
| Clock Tree Insertion Delay Independent Interface App 20120200322 - Block; Stefan ; et al. | 2012-08-09 |
| Generating integrated circuit floorplan layouts Grant 8,219,959 - Dirks , et al. July 10, 2 | 2012-07-10 |
| Generating Integrated Circuit Floorplan Layouts App 20110023000 - Dirks; Juergen ; et al. | 2011-01-27 |
| Config logic power saving method Grant 7,616,517 - Habel , et al. November 10, 2 | 2009-11-10 |
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