Blinne; Richard D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Blinne; Richard D..The latest application filed is for "unified layer stack architecture".

Company Profile

0.9.7

Blinne; Richard D. - Fort Collins CO
Blinne; Richard D. - Ft. Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Unified layer stack architecture Grant 7,853,901 - Lakshmanan , et al. December 14, 2	2010-12-14
Unified Layer Stack Architecture App 20090271755 - Lakshmanan; Viswanathan ; et al.	2009-10-29
Method of automating place and route corrections for an integrated circuit design from physical design validation Grant 7,302,654 - Lakshmanan , et al. November 27, 2	2007-11-27
Method of implementing an engineering change order in an integrated circuit design by windows Grant 7,231,626 - Hoff , et al. June 12, 2	2007-06-12
Method and computer program for verifying an incremental change to an integrated circuit design Grant 7,219,317 - Lakshmanan , et al. May 15, 2	2007-05-15
Method of partitioning an integrated circuit design for physical design verification Grant 7,107,559 - Lakshmanan , et al. September 12, 2	2006-09-12
Method of implementing an engineering change order in an integrated circuit design by windows App 20060136855 - Hoff; Jason K. ; et al.	2006-06-22
Method of automating place and route corrections for an integrated circuit design from physical design validation App 20060095883 - Lakshmanan; Viswanathan ; et al.	2006-05-04
Method of automating place and route corrections for an integrated circuit design from physical design validation App 20060090144 - Lakshmanan; Viswanathan ; et al.	2006-04-27
Method and computer program for verifying an incremental change to an integrated circuit design App 20050235234 - Lakshmanan, Viswanathan ; et al.	2005-10-20
Method of partitioning an integrated circuit design for physical design verification App 20050097488 - Lakshmanan, Viswanathan ; et al.	2005-05-05
Method of repeater insertion for hierarchical integrated circuit design Grant 6,662,349 - Morgan , et al. December 9, 2	2003-12-09
Method of repeater insertion for hierarchical integrated circuit design App 20030163795 - Morgan, David A. ; et al.	2003-08-28
Method for generating format-independent electronic circuit representations Grant 5,995,730 - Blinne November 30, 1	1999-11-30
Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits Grant 5,521,834 - Crafts , et al. May 28, 1	1996-05-28
Method of estimating logic cell delay time Grant 5,274,568 - Blinne , et al. December 28, 1	1993-12-28

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