Blatchford; James Walter

Patent Applications and Registrations

Patent applications and USPTO patent grants for Blatchford; James Walter.The latest application filed is for "sram layout for double patterning".

Company Profile

2.55.47

Blatchford; James Walter - Richardson TX
Blatchford; James Walter - Saratoga Springs NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Sram Layout For Double Patterning App 20210028179 - Blatchford; James Walter	2021-01-28
SRAM layout for double patterning Grant 10,840,250 - Blatchford November 17, 2	2020-11-17
Rectangular via for ensuring via yield in the absence of via redundancy Grant 10,741,489 - Blatchford A	2020-08-11
Sram Layout For Double Patterning App 20190109143 - Blatchford; James Walter	2019-04-11
SRAM layout for double patterning Grant 10,181,474 - Blatchford Ja	2019-01-15
SRAM layout for double patterning Grant 10,103,153 - Blatchford October 16, 2	2018-10-16
Metal on elongated contacts Grant 10,103,171 - Blatchford , et al. October 16, 2	2018-10-16
Elongated contacts using litho-freeze-litho-etch process Grant 10,043,714 - Blatchford , et al. August 7, 2	2018-08-07
Method to form silicide and contact at embedded epitaxial facet Grant 10,008,499 - Lim , et al. June 26, 2	2018-06-26
Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two Grant 9,899,364 - Blatchford , et al. February 20, 2	2018-02-20
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20180047728 - LIM; Kwan-Yong ; et al.	2018-02-15
Method to form silicide and contact at embedded epitaxial facet Grant 9,812,452 - Lim , et al. November 7, 2	2017-11-07
Elongated Contacts Using Litho-freeze-litho-etch Process App 20170178966 - BLATCHFORD; James Walter ; et al.	2017-06-22
Elongated contacts using litho-freeze-litho-etch process Grant 9,620,419 - Blatchford , et al. April 11, 2	2017-04-11
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20170047329 - LIM; Kwan-Yong ; et al.	2017-02-16
Method to form silicide and contact at embedded epitaxial facet Grant 9,508,601 - Lim , et al. November 29, 2	2016-11-29
Metal On Elongated Contacts App 20160190156 - BLATCHFORD; James Walter ; et al.	2016-06-30
Elongated Contacts Using Litho-freeze-litho-etch Process App 20160190016 - BLATCHFORD; James Walter ; et al.	2016-06-30
Metal on elongated contacts Grant 9,312,170 - Blatchford , et al. April 12, 2	2016-04-12
Elongated contacts using litho-freeze-litho-etch process Grant 9,305,848 - Blatchford , et al. April 5, 2	2016-04-05
Sram Layout For Double Patterning App 20160020214 - BLATCHFORD; James Walter	2016-01-21
Layout Method To Minimize Context Effects And Die Area App 20150332974 - Blatchford; James Walter ; et al.	2015-11-19
Layout method to minimize context effects and die area Grant 9,123,562 - Blatchford , et al. September 1, 2	2015-09-01
Method for ensuring DPT compliance for auto-routed via layers Grant 9,112,000 - Blatchford August 18, 2	2015-08-18
Elongated Contacts Using Litho-freeze-litho-etch Process App 20150170975 - BLATCHFORD; James Walter ; et al.	2015-06-18
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20150170972 - LIM; Kwan-Yong ; et al.	2015-06-18
Metal On Elongated Contacts App 20150170962 - BLATCHFORD; James Walter ; et al.	2015-06-18
Two-track cross-connect in double-patterned structure using rectangular via Grant 9,024,450 - Blatchford , et al. May 5, 2	2015-05-05
System for controlling SiGe-to-gate spacing Grant 8,828,833 - Blatchford , et al. September 9, 2	2014-09-09
Method to ensure double patterning technology compliance in standard cells Grant 8,756,550 - Blatchford June 17, 2	2014-06-17
Method for generating ultra-short-run-length dummy poly features Grant 8,751,977 - Blatchford June 10, 2	2014-06-10
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process Grant 8,745,548 - Blatchford June 3, 2	2014-06-03
Method for ensuring DPT compliance with autorouted metal layers Grant 8,707,223 - Blatchford April 22, 2	2014-04-22
Perturbational Technique For Co-optimizing Design Rules And Illumination Conditions For Lithography Process App 20140101622 - BLATCHFORD; James Walter	2014-04-10
Gate CD control using local design on both sides of neighboring dummy gate level features Grant 8,667,432 - Blatchford , et al. March 4, 2	2014-03-04
Gate CD control using local design on both sides of neighboring dummy gate level features Grant 8,663,879 - Blatchford , et al. March 4, 2	2014-03-04
Two-track Cross-connect In Double-patterned Structure Using Rectangular Via App 20140035160 - BLATCHFORD; James Walter ; et al.	2014-02-06
Dual alignment strategy for optimizing contact layer alignment Grant 8,603,905 - Blatchford December 10, 2	2013-12-10
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process Grant 8,607,170 - Blatchford December 10, 2	2013-12-10
Two-track cross-connect in double-patterned structure using rectangular via Grant 8,580,675 - Blatchford , et al. November 12, 2	2013-11-12
Manufacturability enhancements for gate patterning process using polysilicon sub layer Grant 8,584,053 - Blatchford November 12, 2	2013-11-12
Pattern-split decomposition strategy for double-patterned lithography process Grant 8,575,020 - Blatchford November 5, 2	2013-11-05
Gate Cd Control Using Local Design On Both Sides Of Neighboring Dummy Gate Level Features App 20130246983 - BLATCHFORD; James Walter ; et al.	2013-09-19
Gate Cd Control Using Local Design On Both Sides Of Neighboring Dummy Gate Level Features App 20130244144 - BLATCHFORD; James Walter ; et al.	2013-09-19
Flexible integration of logic blocks with transistors of different threshold voltages Grant 8,513,105 - Baldwin , et al. August 20, 2	2013-08-20
Two-track cross-connects in double-patterned metal layers using a forbidden zone Grant 8,461,038 - Blatchford June 11, 2	2013-06-11
Gate CD control using local design on both sides of neighboring dummy gate level features Grant 8,455,180 - Blatchford , et al. June 4, 2	2013-06-04
Illumination And Design Rule Method For Double Patterned Slotted Contacts App 20130069170 - Blatchford; James Walter	2013-03-21
Method For Ensuring DPT Compliance for Auto-Routed Via Layers App 20130072020 - Blatchford; James Walter	2013-03-21
Method To Ensure Double Patterning Technology Compliance In Standard Cells App 20130074029 - Blatchford; James Walter	2013-03-21
Rectangular Via For Ensuring Via Yield In The Absence Of Via Redundancy App 20130069244 - Blatchford; James Walter	2013-03-21
Layout Method To Minimize Context Effects and Die Area App 20130069081 - Blatchford; James Walter ; et al.	2013-03-21
Method For Ensuring Dpt Compliance With Autorouted Metal Layers App 20130074028 - BLATCHFORD; James Walter	2013-03-21
Sram Layout For Double Patterning App 20130069168 - Blatchford; James Walter	2013-03-21
Hybrid pitch-split pattern-split lithography process Grant 8,372,743 - Blatchford February 12, 2	2013-02-12
Manufacturability Enhancements For Gate Patterning Process Using Polysilicon Sub Layer App 20120331425 - Blatchford; James Walter	2012-12-27
Gate line edge roughness reduction by using 2P/2E process together with high temperature bake Grant 8,304,317 - Gu , et al. November 6, 2	2012-11-06
Perturbational Technique For Co-optimizing Design Rules And Illumination Conditions For Lithography Process App 20120227015 - Blatchford; James Walter	2012-09-06
Two-track Cross-connect In Double-patterned Structure Using Rectangular Via App 20120223439 - Blatchford; James Walter ; et al.	2012-09-06
Pattern-split Decomposition Strategy For Double-patterned Lithography Process App 20120225551 - Blatchford; James Walter	2012-09-06
Hybrid Pitch-split Pattern-split Lithography Process App 20120225550 - Blatchford; James Walter	2012-09-06
Two-track Cross-connects In Double-patterned Metal Layers Using A Forbidden Zone App 20120225552 - Blatchford; James Walter	2012-09-06
Diagonal Interconnect For Improved Process Margin With Off-axis Illumination App 20120148942 - Blatchford; James Walter	2012-06-14
Method For Generating Ultra-short-run-length Dummy Poly Features App 20120131522 - Blatchford; James Walter	2012-05-24
Layout of printable assist features to aid transistor control Grant 8,176,443 - Rathsack , et al. May 8, 2	2012-05-08
Gate Cd Control Using Local Design On Both Sides Of Neighboring Dummy Gate Level Features App 20120107729 - Blatchford; James Walter ; et al.	2012-05-03
ICs with end gates having adjacent electrically connected field poly Grant 8,138,074 - Blatchford March 20, 2	2012-03-20
Method for layout of random via arrays in the presence of strong pitch restrictions Grant 8,051,391 - Blatchford November 1, 2	2011-11-01
System and method for making photomasks Grant 7,930,656 - Aton , et al. April 19, 2	2011-04-19
Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach Grant 7,910,289 - Rathsack , et al. March 22, 2	2011-03-22
EDA methodology for extending ghost feature beyond notched active to improve adjacent gate CD control using a two-print-two-etch approach Grant 7,807,343 - Rathsack , et al. October 5, 2	2010-10-05
Method of achieving dense-pitch interconnect patterning in integrated circuits Grant 7,790,525 - Prins , et al. September 7, 2	2010-09-07
Methods for adjusting shifter width of an alternating phase shifter having variable width Grant 7,774,739 - Blatchford , et al. August 10, 2	2010-08-10
Gate line edge roughness reduction by using 2P/2E process together with high temperature bake App 20100167484 - Gu; Yiming ; et al.	2010-07-01
Dual Alignment Strategy For Optimizing Contact Layer Alignment App 20100167513 - Blatchford; James Walter	2010-07-01
Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements Grant 7,745,067 - Blatchford , et al. June 29, 2	2010-06-29
Two-print two-etch method for enhancement of CD control using ghost poly Grant 7,737,016 - Blatchford , et al. June 15, 2	2010-06-15
Method For Layout Of Random Via Arrays In The Presence Of Strong Pitch Restrictions App 20100031216 - BLATCHFORD; James Walter	2010-02-04
Design Layout Of Printable Assist Features To Aid Transistor Control App 20090300567 - Rathsack; Benjamen Michael ; et al.	2009-12-03
Gate critical dimension variation by use of ghost features Grant 7,569,309 - Blatchford , et al. August 4, 2	2009-08-04
System And Method For Making Photomasks App 20090125865 - Aton; Thomas J. ; et al.	2009-05-14
Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits App 20090101983 - Prins; Steven Lee ; et al.	2009-04-23
Eda Methodology For Extending Ghost Feature Beyond Notched Active To Improve Adjacent Gate Cd Control Using A Two-print-two-etch Approach App 20080166889 - Rathsack; Benjamen Michael ; et al.	2008-07-10
Maximum/variable Shifter Widths To Allow Alternating Phase-shift Implementation For Dense Or Existing Layouts App 20080134128 - BLATCHFORD; James Walter ; et al.	2008-06-05
Two-print-two-etch method for enhancement of CD control using ghost poly App 20080014684 - Blatchford; James Walter ; et al.	2008-01-17
Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach App 20070161245 - Rathsack; Benjamen Michael ; et al.	2007-07-12
Gate critical dimension variation by use of ghost features App 20070105387 - Blatchford; James Walter ; et al.	2007-05-10
Reduction of mechanical stress on pattern specific geometries during etch using double pattern layout and process approach App 20070099424 - Rathsack; Benjamen Michael ; et al.	2007-05-03
Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements App 20070028200 - Blatchford; James Walter ; et al.	2007-02-01
Layout modification to eliminate line bending caused by line material shrinkage App 20060292885 - Ukraintsev; Vladimir Alexeevich ; et al.	2006-12-28

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