loadpatents
name:-0.030581951141357
name:-0.097273111343384
name:-0.028898954391479
Blaner; Bartholomew Patent Filings

Blaner; Bartholomew

Patent Applications and Registrations

Patent applications and USPTO patent grants for Blaner; Bartholomew.The latest application filed is for "speculative data processing and recovery".

Company Profile
34.101.77
  • Blaner; Bartholomew - Shelburne VT
  • Blaner; Bartholomew - Underhill Center VT
  • Blaner; Bartholomew - Underhill VT US
  • Blaner; Bartholomew - Newark Valley NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Promotion of ERAT cache entries
Grant 11,221,957 - Blaner , et al. January 11, 2
2022-01-11
Translation invalidation in a translation cache serving an accelerator
Grant 11,113,204 - Blaner , et al. September 7, 2
2021-09-07
Integrated circuit and data processing system supporting address aliasing in an accelerator
Grant 11,030,110 - Siegel , et al. June 8, 2
2021-06-08
Speculative data processing and recovery
Grant 10,936,402 - Abali , et al. March 2, 2
2021-03-02
Speculative checkin of ERAT cache entries
Grant 10,884,943 - Blaner , et al. January 5, 2
2021-01-05
Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
Grant 10,846,235 - Blaner , et al. November 24, 2
2020-11-24
Live partition mobility enabled hardware accelerator address translation fault resolution
Grant 10,831,593 - Arimilli , et al. November 10, 2
2020-11-10
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements
Grant 10,824,585 - Balakrishnan , et al. November 3, 2
2020-11-03
Reconfigurable array processor for pattern matching
Grant 10,824,953 - Abali , et al. November 3, 2
2020-11-03
Reconfigurable array processor for pattern matching
Grant 10,824,952 - Abali , et al. November 3, 2
2020-11-03
Efficient and accurate lookups of data by a stream processor using a hash table
Grant 10,817,491 - Abali , et al. October 27, 2
2020-10-27
Efficient and accurate lookups of data by a stream processor using a hash table
Grant 10,803,040 - Abali , et al. October 13, 2
2020-10-13
Integrated circuit and data processing system having a configurable cache directory for an accelerator
Grant 10,761,995 - Blaner , et al. Sep
2020-09-01
Updating cache using two bloom filters
Grant 10,698,812 - Bar-Joshua , et al.
2020-06-30
Speculative Data Processing And Recovery
App 20200167224 - Abali; Bulent ;   et al.
2020-05-28
Maintaining consistency between address translations in a data processing system
Grant 10,599,569 - Blaner , et al.
2020-03-24
Managed hardware accelerator address translation fault resolution utilizing a credit
Grant 10,585,744 - Arimilli , et al.
2020-03-10
Promotion Of Erat Cache Entries
App 20200073817 - Blaner; Bartholomew ;   et al.
2020-03-05
Speculative Checkin Of Erat Cache Entries
App 20200073816 - Blaner; Bartholomew ;   et al.
2020-03-05
Live partition mobility enabled hardware accelerator address translation fault resolution
Grant 10,572,337 - Arimilli , et al. Feb
2020-02-25
Updating cache using two bloom filters
Grant 10,572,381 - Bar-Joshua , et al. Feb
2020-02-25
Updating cache using two bloom filters
Grant 10,565,102 - Bar-Joshua , et al. Feb
2020-02-18
Updating cache using two bloom filters
Grant 10,552,313 - Bar-Joshua , et al. Fe
2020-02-04
Managed hardware accelerator address translation fault resolution utilizing a credit
Grant 10,545,816 - Arimilli , et al. Ja
2020-01-28
Hardware accelerator address translation fault resolution
Grant 10,528,418 - Arimilli , et al. J
2020-01-07
Updating Cache Using Two Bloom Filters
App 20190377673 - Bar-Joshua; Michael ;   et al.
2019-12-12
Translation Invalidation In A Translation Cache Serving An Accelerator
App 20190332548 - BLANER; BARTHOLOMEW ;   et al.
2019-10-31
Integrated Circuit And Data Processing System Having A Configurable Cache Directory For An Accelerator
App 20190332549 - BLANER; BARTHOLOMEW ;   et al.
2019-10-31
Integrated Circuit And Data Processing System Supporting Address Aliasing In An Accelerator
App 20190332551 - SIEGEL; MICHAEL S. ;   et al.
2019-10-31
Integrated Circuit And Data Processing System Supporting Attachment Of A Real Address-agnostic Accelerator
App 20190332537 - BLANER; BARTHOLOMEW ;   et al.
2019-10-31
Managing lowest point of coherency (LPC) memory using a service layer adapter
Grant 10,394,711 - Adar , et al. A
2019-08-27
Suspend and resume in a time shared coprocessor
Grant 10,380,048 - Abali , et al. A
2019-08-13
In-place data compression with small working memory
Grant 10,374,628 - Abali , et al.
2019-08-06
Memory move instruction sequence targeting an accelerator switchboard
Grant 10,346,164 - Arimilli , et al. July 9, 2
2019-07-09
Live Partition Mobility Enabled Hardware Accelerator Address Translation Fault Resolution
App 20190155683 - Arimilli; Lakshminarayana B. ;   et al.
2019-05-23
Hardware accelerator address translation fault resolution
Grant 10,289,479 - Arimilli , et al.
2019-05-14
Efficient And Accurate Lookups Of Data By A Stream Processor Using A Hash Table
App 20190065493 - ABALI; BULENT ;   et al.
2019-02-28
Efficient And Accurate Lookups Of Data By A Stream Processor Using A Hash Table
App 20190065494 - ABALI; BULENT ;   et al.
2019-02-28
Pre-transmission data reordering for a serial interface
Grant 10,216,653 - Arimilli , et al. Feb
2019-02-26
Live partition mobility enabled hardware accelerator address translation fault resolution
Grant 10,216,568 - Arimilli , et al. Feb
2019-02-26
Updating Cache Using Two Bloom Filters
App 20190026221 - Bar-Joshua; Michael ;   et al.
2019-01-24
Updating Cache Using Two Bloom Filters
App 20190026218 - Bar-Joshua; Michael ;   et al.
2019-01-24
Updating Cache Using Two Bloom Filters
App 20190026219 - Bar-Joshua; Michael ;   et al.
2019-01-24
Comparison-based Sort In A Reconfigurable Array Processor Having Multiple Processing Elements For Sorting Array Elements
App 20190012169 - Balakrishnan; Ganesh ;   et al.
2019-01-10
Live Partition Mobility Enabled Hardware Accelerator Address Translation Fault Resolution
App 20180314588 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Managed Hardware Accelerator Address Translation Fault Resolution Utilizing a Credit
App 20180314584 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Hardware Accelerator Address Translation Fault Resolution
App 20180314583 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Managed Hardware Accelerator Address Translation Fault Resolution Utilizing a Credit
App 20180314582 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Live Partition Mobility Enabled Hardware Accelerator Address Translation Fault Resolution
App 20180314589 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Hardware Accelerator Address Translation Fault Resolution
App 20180314581 - Arimilli; Lakshminarayana B. ;   et al.
2018-11-01
Maintaining Agent Inclusivity Within A Distributed Mmu
App 20180300256 - BLANER; BARTHOLOMEW ;   et al.
2018-10-18
Maintaining Agent Inclusivity Within A Distributed Mmu
App 20180300255 - BLANER; BARTHOLOMEW ;   et al.
2018-10-18
In-place Data Compression With Small Working Memory
App 20180293028 - Abali; Bulent ;   et al.
2018-10-11
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements
Grant 10,078,513 - Balakrishnan , et al. September 18, 2
2018-09-18
Managing Lowest Point Of Coherency (lpc) Memory Using A Service Layer Adapter
App 20180150396 - ADAR; ETAI ;   et al.
2018-05-31
Data compression accelerator methods, apparatus and design structure with improved resource utilization
Grant 9,971,704 - Abali , et al. May 15, 2
2018-05-15
Concurrent error detection in a ternary content-addressable memory (TCAM) device
Grant 9,940,191 - Abali , et al. April 10, 2
2018-04-10
Pre-transmission Data Reordering For A Serial Interface
App 20180095905 - ARIMILLI; LAKSHMINARAYANA BABA ;   et al.
2018-04-05
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements
Grant 9,934,030 - Balakrishnan , et al. April 3, 2
2018-04-03
Suspend And Resume In A Time Shared Coprocessor
App 20180081839 - Abali; Bulent ;   et al.
2018-03-22
Suspend and resume in a time shared coprocessor
Grant 9,921,986 - Abali , et al. March 20, 2
2018-03-20
Comparison-based Sort In A Reconfigurable Array Processor Having Multiple Processing Elements For Sorting Array Elements
App 20180060070 - Balakrishnan; Ganesh ;   et al.
2018-03-01
Memory Move Instruction Sequence Targeting An Accelerator Switchboard
App 20180052688 - ARIMILLI; LAKSHMINARAYANA B. ;   et al.
2018-02-22
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements
Grant 9,891,912 - Balakrishnan , et al. February 13, 2
2018-02-13
Techniques For Maintaining Consistency Between Address Translations In A Data Processing System
App 20170371789 - BLANER; BARTHOLOMEW ;   et al.
2017-12-28
Suspend and resume in a time shared coprocessor
Grant 9,852,095 - Abali , et al. December 26, 2
2017-12-26
Tracking memory accesses when invalidating effective address to real address translations
Grant 9,740,629 - Blaner , et al. August 22, 2
2017-08-22
Tracking memory accesses when invalidating effective address to real address translations
Grant 9,727,483 - Blaner , et al. August 8, 2
2017-08-08
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
Grant 9,710,310 - Bass , et al. July 18, 2
2017-07-18
Suspend And Resume In A Time Shared Coprocessor
App 20170116142 - Abali; Bulent ;   et al.
2017-04-27
Suspend And Resume In A Time Shared Coprocessor
App 20170115924 - Abali; Bulent ;   et al.
2017-04-27
Operation of a multi-slice processor implementing priority encoding of data pattern matches
Grant 9,628,109 - Abali , et al. April 18, 2
2017-04-18
Concurrent error detection in a ternary content-addressable memory (TCAM) device
Grant 9,606,861 - Abali , et al. March 28, 2
2017-03-28
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
Grant 9,606,838 - Bass , et al. March 28, 2
2017-03-28
Selection of post-request action based on combined response and input from the request source
Grant 9,606,922 - Blaner , et al. March 28, 2
2017-03-28
Creating a dynamic Huffman table
Grant 9,584,156 - Abali , et al. February 28, 2
2017-02-28
Random number generation security
Grant 9,575,728 - Blaner , et al. February 21, 2
2017-02-21
Selection of post-request action based on combined response and input from the request source
Grant 9,547,597 - Blaner , et al. January 17, 2
2017-01-17
Data Compression Accelerator Methods, Apparatus and Design Structure with Improved Resource Utilization
App 20160283398 - Abali; Bulent ;   et al.
2016-09-29
Concurrent Error Detection In A Ternary Content-addressable Memory (tcam) Device
App 20160283317 - Abali; Bulent ;   et al.
2016-09-29
Concurrent Error Detection In A Ternary Content-addressable Memory (tcam) Device
App 20160283316 - Abali; Bulent ;   et al.
2016-09-29
Integrated circuit system having decoupled logical and physical interfaces
Grant 9,454,484 - Blaner , et al. September 27, 2
2016-09-27
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
Grant 9,448,846 - Bass , et al. September 20, 2
2016-09-20
Programmable coherent proxy for attached processor
Grant 9,442,852 - Blaner , et al. September 13, 2
2016-09-13
Techniques for improving random number generation security
Grant 9,417,846 - Blaner , et al. August 16, 2
2016-08-16
Coherent attached processor proxy supporting coherence state update in presence of dispatched master
Grant 9,390,013 - Blaner , et al. July 12, 2
2016-07-12
Tracking Memory Accesses When Invalidating Effective Address To Real Address Translations
App 20160179698 - Blaner; Bartholomew ;   et al.
2016-06-23
Tracking Memory Accesses When Invalidating Effective Address To Real Address Translations
App 20160179694 - Blaner; Bartholomew ;   et al.
2016-06-23
Programmable coherent proxy for attached processor
Grant 9,367,458 - Blaner , et al. June 14, 2
2016-06-14
Comparison-based Sort In An Array Processor
App 20160124900 - Balakrishnan; Ganesh ;   et al.
2016-05-05
Comparison-based Sort In An Array Processor
App 20160124755 - Balakrishnan; Ganesh ;   et al.
2016-05-05
Reconfigurable Array Processor For Pattern Matching
App 20160085720 - Abali; Bulent ;   et al.
2016-03-24
Reconfigurable Array Processor For Pattern Matching
App 20160085721 - Abali; Bulent ;   et al.
2016-03-24
Termination of requests in a distributed coprocessor system
Grant 9,286,129 - Bass , et al. March 15, 2
2016-03-15
Coherent attached processor proxy supporting coherence state update in presence of dispatched master
Grant 9,256,537 - Blaner , et al. February 9, 2
2016-02-09
Epoch-based recovery for coherent attached processor proxy
Grant 9,251,076 - Blaner , et al. February 2, 2
2016-02-02
Accelerated recovery for snooped addresses in a coherent attached processor proxy
Grant 9,251,077 - Blaner , et al. February 2, 2
2016-02-02
Parallel huffman decoder
Grant 9,252,805 - Abali , et al. February 2, 2
2016-02-02
Data recovery for coherent attached processor proxy
Grant 9,229,868 - Blaner , et al. January 5, 2
2016-01-05
Dynamically Configurable Hardware Queues For Dispatching Jobs To A Plurality Of Hardware Acceleration Engines
App 20150355948 - Bass; Brian M. ;   et al.
2015-12-10
Dynamically Configurable Hardware Queues For Dispatching Jobs To A Plurality Of Hardware Acceleration Engines
App 20150355949 - Bass; Brian M. ;   et al.
2015-12-10
Coherent attached processor proxy having hybrid directory
Grant 9,208,092 - Blaner , et al. December 8, 2
2015-12-08
Coherent attached processor proxy having hybrid directory
Grant 9,208,091 - Blaner , et al. December 8, 2
2015-12-08
Coherent attached processor proxy supporting master parking
Grant 9,146,872 - Blaner , et al. September 29, 2
2015-09-29
Coherent attached processor proxy supporting master parking
Grant 9,135,174 - Blaner , et al. September 15, 2
2015-09-15
Coherent proxy for attached processor
Grant 9,086,975 - Blaner , et al. July 21, 2
2015-07-21
Epoch-based recovery for coherent attached processor proxy
Grant 9,021,211 - Blaner , et al. April 28, 2
2015-04-28
Accelerated recovery for snooped addresses in a coherent attached processor proxy
Grant 8,990,513 - Blaner , et al. March 24, 2
2015-03-24
Data recovery for coherent attached processor proxy
Grant 8,938,587 - Blaner , et al. January 20, 2
2015-01-20
Coherent Attached Processor Proxy Having Hybrid Directory
App 20140379997 - Blaner; Bartholomew ;   et al.
2014-12-25
Coherent Attached Processor Proxy Having Hybrid Directory
App 20140379989 - Blaner; Bartholomew ;   et al.
2014-12-25
Integrated Circuit System Having Decoupled Logical And Physical Interfaces
App 20140365733 - BLANER; BARTHOLOMEW ;   et al.
2014-12-11
Termination of Requests in a Distributed Coprocessor System
App 20140337855 - Bass; Brian Mitchell ;   et al.
2014-11-13
Selection Of Post-request Action Based On Combined Response And Input From The Request Source
App 20140250275 - BLANER; BARTHOLOMEW ;   et al.
2014-09-04
Selection Of Post-request Action Based On Combined Response And Input From The Request Source
App 20140250276 - BLANER; BARTHOLOMEW ;   et al.
2014-09-04
Coherent Attached Processor Proxy Supporting Coherence State Update In Presence Of Dispatched Master
App 20140229685 - Blaner; Bartholomew ;   et al.
2014-08-14
Coherent Attached Processor Proxy Supporting Coherence State Update In Presence Of Dispatched Master
App 20140229684 - Blaner; Bartholomew ;   et al.
2014-08-14
Accelerated Recovery For Snooped Addresses In A Coherent Attached Processor Proxy
App 20140201468 - BLANER; BARTHOLOMEW ;   et al.
2014-07-17
Data Recovery For Coherent Attached Processor Proxy
App 20140201460 - BLANER; BARTHOLOMEW ;   et al.
2014-07-17
Data Recovery For Coherent Attached Processor Proxy
App 20140201466 - BLANER; BARTHOLOMEW ;   et al.
2014-07-17
Epoch-based Recovery For Coherent Attached Processor Proxy
App 20140201464 - Blaner; Bartholomew ;   et al.
2014-07-17
Accelerated Recovery For Snooped Addresses In A Coherent Attached Processor Proxy
App 20140201465 - Blaner; Bartholomew ;   et al.
2014-07-17
Epoch-based Recovery For Coherent Attached Processor Proxy
App 20140201467 - BLANER; Bartholomew ;   et al.
2014-07-17
Coherent Attached Processor Proxy Supporting Master Parking
App 20140149688 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Programmable Coherent Proxy For Attached Processor
App 20140149683 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Coherent Attached Processor Proxy Supporting Master Parking
App 20140149686 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Programmable Coherent Proxy For Attached Processor
App 20140149682 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Coherent Proxy For Attached Processor
App 20140149681 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Coherent Proxy For Attached Processor
App 20140149689 - BLANER; BARTHOLOMEW ;   et al.
2014-05-29
Shared parallel adder tree for executing multiple different population count operations
Grant 8,661,072 - Blaner , et al. February 25, 2
2014-02-25
Unpacking a variable number of data bits
Grant 8,587,458 - Abali , et al. November 19, 2
2013-11-19
Unpacking A Variable Number Of Data Bits
App 20130147643 - ABALI; Bulent ;   et al.
2013-06-13
Dynamically Configurable Hardware Queues For Dispatching Jobs To A Plurality Of Hardware Acceleration Engines
App 20130152099 - Bass; Brian Mitchell ;   et al.
2013-06-13
Method for predictive decoding of a load tagged pointer instruction
Grant 8,166,279 - Blaner , et al. April 24, 2
2012-04-24
Structure for predictive decoding
Grant 8,095,777 - Blaner , et al. January 10, 2
2012-01-10
Structure for implementing speculative clock gating of digital logic circuits
Grant 8,078,999 - Blaner , et al. December 13, 2
2011-12-13
Apparatus and method for implementing speculative clock gating of digital logic circuits
Grant 7,971,161 - Blaner , et al. June 28, 2
2011-06-28
Method and structure for low latency load-tagged pointer instruction for computer microarchitechture
Grant 7,849,293 - Blaner , et al. December 7, 2
2010-12-07
Shared Parallel Adder Tree For Executing Multiple Different Population Count Operations
App 20100049779 - Blaner; Bartholomew ;   et al.
2010-02-25
Method And Structure For Low Latency Load-tagged Pointer Instruction For Computer Microarchitechture
App 20090198967 - Blaner; Bartholomew ;   et al.
2009-08-06
Apparatus And Method For Implementing Speculative Clock Gating Of Digital Logic Circuits
App 20090193281 - Blaner; Bartholomew ;   et al.
2009-07-30
Design Structure For Implementing Speculative Clock Gating Of Digital Logic Circuits
App 20090193283 - Blaner; Bartholomew ;   et al.
2009-07-30
Design Structure For Predictive Decoding
App 20090119494 - Blaner; Bartholomew ;   et al.
2009-05-07
Facilitating inter-DSP data communications
Grant 7,519,793 - Abdelilah , et al. April 14, 2
2009-04-14
Method And Apparatus For Predictive Decoding
App 20080276069 - Blaner; Bartholomew ;   et al.
2008-11-06
Facilitating Inter-DSP Data Communications
App 20080072005 - Abdelilah; Youseff ;   et al.
2008-03-20
Facilitating inter-DSP data communications
Grant 7,325,122 - Abdelilah , et al. January 29, 2
2008-01-29
Facilitating Inter-DSP Data Communications
App 20080010390 - Abdelilah; Youseff ;   et al.
2008-01-10
Facilitating inter-DSP data communications
App 20050188129 - Abdelilah, Youseff ;   et al.
2005-08-25
System and method for system initializating a data processing system by selecting parameters from one of a user-defined input, a serial non-volatile memory and a parallel non-volatile memory
Grant 6,857,065 - Blaner , et al. February 15, 2
2005-02-15
System and method for data processing system initialization
App 20030009655 - Blaner, Bartholomew ;   et al.
2003-01-09
Real time invariant behavior cache
Grant 6,157,981 - Blaner , et al. December 5, 2
2000-12-05
Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache
Grant 6,029,240 - Blaner , et al. February 22, 2
2000-02-22
System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories
Grant 5,732,234 - Vassiliadis , et al. March 24, 1
1998-03-24
Multiple condition code branching system in a multi-processor environment
Grant 5,659,722 - Blaner , et al. August 19, 1
1997-08-19
Status predictor for combined shifter-rotate/merge unit
Grant 5,590,348 - Phillips , et al. December 31, 1
1996-12-31
System for executing scalar instructions in parallel based on control bits appended by compounding decoder
Grant 5,504,932 - Vassiliadis , et al. April 2, 1
1996-04-02
System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions
Grant 5,502,826 - Vassiliadis , et al. March 26, 1
1996-03-26
Cache store of instruction pairs with tags to indicate parallel execution
Grant 5,475,853 - Blaner , et al. December 12, 1
1995-12-12
Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode
Grant 5,471,628 - Phillips , et al. November 28, 1
1995-11-28
Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
Grant 5,465,377 - Blaner , et al. November 7, 1
1995-11-07
Predecode instruction compounding
Grant 5,459,844 - Eickemeyer , et al. October 17, 1
1995-10-17
Cross-cache-line compounding algorithm for scism processors
Grant 5,446,850 - Jeremiah , et al. August 29, 1
1995-08-29
Apparatus for initializing branch prediction information
Grant 5,423,011 - Blaner , et al. June 6, 1
1995-06-06
Computer system accelerator for multi-word cross-boundary storage access
Grant 5,386,531 - Blaner , et al. January 31, 1
1995-01-31
In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution
Grant 5,355,460 - Eickemeyer , et al. October 11, 1
1994-10-11
System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag
Grant 5,303,356 - Vassiliadis , et al. April 12, 1
1994-04-12
Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
Grant 5,295,249 - Blaner , et al. March 15, 1
1994-03-15
Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
Grant 5,214,763 - Blaner , et al. May 25, 1
1993-05-25
Memory management for scalable compound instruction set machines with in-memory compounding
Grant 5,197,135 - Eickemeyer , et al. March 23, 1
1993-03-23
Data dependency collapsing hardware apparatus
Grant 5,051,940 - Vassiliadis , et al. September 24, 1
1991-09-24
Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means
Grant 5,003,462 - Blaner , et al. March 26, 1
1991-03-26
Packet switch network protocol
Grant 4,862,461 - Blaner August 29, 1
1989-08-29

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