Bjorkman; Claes H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bjorkman; Claes H..The latest application filed is for "method and system for wafer level singulation".

Company Profile

0.16.14

Bjorkman; Claes H. - Los Altos CA
Bjorkman; Claes H. - Mountain View CA
Bjorkman; Claes H. - Los Alto CA
Bjorkman, Claes H. - Lost Altos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for wafer level singulation Grant 9,502,294 - Schuegraf , et al. November 22, 2	2016-11-22
Method And System For Wafer Level Singulation App 20140196850 - Schuegraf; Klaus ; et al.	2014-07-17
Method and system for wafer level singulation Grant 8,580,615 - Schuegraf , et al. November 12, 2	2013-11-12
Method And System For Wafer Level Singulation App 20130045570 - Schuegraf; Klaus ; et al.	2013-02-21
Uniform magnetically enhanced reactive ion etching using nested electromagnetic coils Grant 7,458,335 - Bjorkman December 2, 2	2008-12-02
Methods And Apparatus For Transferring Conductive Pieces During Semiconductor Device Fabrication App 20080283387 - Rice; Michael R. ; et al.	2008-11-20
Methods and apparatus for transferring conductive pieces during semiconductor device fabrication Grant 7,407,081 - Rice , et al. August 5, 2	2008-08-05
Integrated low k dielectrics and etch stops Grant 7,227,244 - Bjorkman , et al. June 5, 2	2007-06-05
Ashable layers for reducing critical dimensions of integrated circuit features Grant 7,105,442 - Shan , et al. September 12, 2	2006-09-12
Methods and apparatus for transferring conductive pieces during semiconductor device fabrication App 20050232728 - Rice, Michael R. ; et al.	2005-10-20
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene Grant 6,949,203 - Hsieh , et al. September 27, 2	2005-09-27
Integrated method for release and passivation of MEMS structures Grant 6,902,947 - Chinn , et al. June 7, 2	2005-06-07
Integrated low K dielectrics and etch stops Grant 6,858,153 - Bjorkman , et al. February 22, 2	2005-02-22
Integrated low k dielectrics and etch stops App 20050023694 - Bjorkman, Claes H. ; et al.	2005-02-03
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene Grant 6,793,835 - Luo , et al. September 21, 2	2004-09-21
Flash step preparatory to dielectric etch Grant 6,787,475 - Wang , et al. September 7, 2	2004-09-07
Integrated method for release and passivation of MEMS structures App 20040033639 - Chinn, Jeffrey D. ; et al.	2004-02-19
Method of etching a trench in a silicon-containing dielectric material Grant 6,686,293 - Kim , et al. February 3, 2	2004-02-03
Integrated low k dielectrics and etch stops Grant 6,669,858 - Bjorkman , et al. December 30, 2	2003-12-30
Ashable layers for reducing critical dimensions of integrated circuit features App 20030219988 - Shan, Hongqing ; et al.	2003-11-27
Method Of Etching A Trench In A Silicon-containing Dielectric Material App 20030211750 - Kim, Yunsang ; et al.	2003-11-13
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene App 20030164354 - Hsieh, Chang-Lin ; et al.	2003-09-04
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene App 20030057179 - Luo, Lee ; et al.	2003-03-27
Flash step preparatory to dielectric etch App 20030045116 - Wang, Zhuxu ; et al.	2003-03-06
System level in-situ integrated dielectric etch process particularly useful for copper dual damascene Grant 6,500,357 - Luo , et al. December 31, 2	2002-12-31
Intergrated low k dielectrics and etch stops App 20020084257 - Bjorkman, Claes H. ; et al.	2002-07-04
Integrated low k dielectrics and etch stops App 20020074309 - Bjorkman, Claes H. ; et al.	2002-06-20
Integrated low K dielectrics and etch stops Grant 6,340,435 - Bjorkman , et al. January 22, 2	2002-01-22

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