Bisht; Chetan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bisht; Chetan.The latest application filed is for "integrated circuit layout wiring for multi-core chips".
- Bisht; Chetan - Duluth GA
| Patent | Date |
|---|---|
| Integrated circuit layout wiring for multi-core chips Grant 10,812,079 - Bisht , et al. October 20, 2 | 2020-10-20 |
| Channel-less integrated circuit layout wiring for chips including a plurality of partitions Grant 10,747,933 - Bisht , et al. A | 2020-08-18 |
| Integrated Circuit Layout Wiring For Multi-core Chips App 20190068193 - BISHT; Chetan ; et al. | 2019-02-28 |
| Integrated Circuit Layout Wiring For Multi-core Chips App 20190057178 - BISHT; Chetan ; et al. | 2019-02-21 |
| Integrated circuit layout wiring for multi-core chips Grant 10,102,327 - Bisht , et al. October 16, 2 | 2018-10-16 |
| Integrated circuit layout wiring for multi-core chips Grant 10,097,182 - Bisht , et al. October 9, 2 | 2018-10-09 |
| Integrated Circuit Layout Wiring For Multi-core Chips App 20160188777 - Bisht; Chetan ; et al. | 2016-06-30 |
| Integrated Circuit Layout Wiring For Multi-core Chips App 20160191058 - BISHT; Chetan ; et al. | 2016-06-30 |
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