| Patent | Date |
|---|
Coordinating width changes for an active network link
Grant 10,491,472 - Rothermel , et al. Nov | 2019-11-26 |
Exascale fabric time synchronization
Grant 10,372,647 - Lovett , et al. | 2019-08-06 |
Reliable transport of ethernet packet data with wire-speed and packet data rate match
Grant 10,305,802 - Birrittella , et al. | 2019-05-28 |
Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks
Grant 10,230,665 - Lovett , et al. | 2019-03-12 |
Coordinating Width Changes For An Active Network Link
App 20180191570 - ROTHERMEL; Brent R. ; et al. | 2018-07-05 |
Multichip package link
Grant 9,946,676 - Wagh , et al. April 17, 2 | 2018-04-17 |
Lane error detection and lane removal mechanism to reduce the probability of data corruption
Grant 9,887,804 - Birrittella February 6, 2 | 2018-02-06 |
Efficient link layer retry protocol utilizing implicit acknowledgements
Grant 9,819,452 - Birrittella November 14, 2 | 2017-11-14 |
Reliable Transport Of Ethernet Packet Data With Wire-speed And Packet Data Rate Match
App 20170237659 - Birrittella; Mark S ; et al. | 2017-08-17 |
Exascale Fabric Time Synchronization
App 20170177527 - LOVETT; THOMAS D. ; et al. | 2017-06-22 |
Reliable transport of ethernet packet data with wire-speed and packet data rate match
Grant 9,628,382 - Birrittella , et al. April 18, 2 | 2017-04-18 |
Efficient Link Layer Retry Protocol Utilizing Implicit Acknowledgements
App 20170026150 - Birrittella; Mark S. | 2017-01-26 |
Lane Error Detection And Lane Removal Mechanism To Reduce The Probability Of Data Corruption
App 20170026149 - Birrittella; Mark S. | 2017-01-26 |
Multichip Package Link
App 20160283429 - Wagh; Mahesh ; et al. | 2016-09-29 |
Efficient link layer retry protocol utilizing implicit acknowledgements
Grant 9,397,792 - Birrittella July 19, 2 | 2016-07-19 |
Link Layer Signal Synchronization
App 20160132072 - Birrittella; Mark S. | 2016-05-12 |
Lane error detection and lane removal mechanism to reduce the probability of data corruption
Grant 9,325,449 - Birrittella April 26, 2 | 2016-04-26 |
Link transfer, bit error detection and link retry using flit bundles asynchronous to link fabric packets
Grant 9,306,863 - Birrittella April 5, 2 | 2016-04-05 |
Transport Of Ethernet Packet Data With Wire-speed And Packet Data Rate Match
App 20150222533 - Birrittella; Mark S. ; et al. | 2015-08-06 |
Hierarchical/lossless Packet Preemption To Reduce Latency Jitter In Flow-controlled Packet-based Networks
App 20150180799 - Lovett; Thomas D. ; et al. | 2015-06-25 |
Link Transfer, Bit Error Detection And Link Retry Using Flit Bundles Asynchronous To Link Fabric Packets
App 20150163170 - Birrittella; Mark S. | 2015-06-11 |
Lane Error Detection And Lane Removal Mechanism To Reduce The Probability Of Data Corruption
App 20150163014 - Birrittella; Mark S. | 2015-06-11 |
Efficient Link Layer Retry Protocol Utilizing Implicit Acknowledgements
App 20150163019 - Birrittella; Mark S. | 2015-06-11 |
Transistor level verilog
Grant 7,587,305 - Lutz , et al. September 8, 2 | 2009-09-08 |
Clock signal duty cycle adjust circuit
Grant 6,992,515 - Birrittella January 31, 2 | 2006-01-31 |
Systems and methods for phase detector circuit with reduced offset
Grant 6,836,153 - Birrittella December 28, 2 | 2004-12-28 |
Circuit design for high-speed digital communication
Grant 6,775,339 - Wildes , et al. August 10, 2 | 2004-08-10 |
Systems and methods for phase detector circuit with reduced offset
App 20040150446 - Birrittella, Mark S. | 2004-08-05 |
Transistor level verilog
App 20040002846 - Lutz, Robert J. ; et al. | 2004-01-01 |
Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor
Grant 6,266,759 - Birrittella July 24, 2 | 2001-07-24 |
Networked multiprocessor system with global distributed memory and block transfer engine
Grant 5,797,035 - Birrittella , et al. August 18, 1 | 1998-08-18 |
System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel
Grant 5,583,990 - Birrittella , et al. December 10, 1 | 1996-12-10 |
Fabricating a semiconductor device with buried oxide
Grant 4,717,677 - McLaughlin , et al. January 5, 1 | 1988-01-05 |
Bipolar RAM cell
Grant 4,697,251 - Birrittella , et al. September 29, 1 | 1987-09-29 |
Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers
Grant 4,663,831 - Birrittella , et al. May 12, 1 | 1987-05-12 |
Bipolar ram cell and process
Grant 4,656,495 - Birrittella April 7, 1 | 1987-04-07 |
Gallium arsenide bipolar ECL circuit structure
Grant 4,649,411 - Birrittella March 10, 1 | 1987-03-10 |
ECL to TTL voltage level translator
Grant 4,644,194 - Birrittella , et al. February 17, 1 | 1987-02-17 |
Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
Grant 4,631,570 - Birrittella , et al. December 23, 1 | 1986-12-23 |
NPN bandgap voltage generator
Grant 4,628,248 - Birrittella , et al. December 9, 1 | 1986-12-09 |
Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact
Grant 4,593,457 - Birrittella June 10, 1 | 1986-06-10 |
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