Birman; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Birman; Mark.The latest application filed is for "hybrid memory for search operations".

Company Profile

0.19.7

Birman; Mark - Los Altos CA
Birman; Mark - Palo Alto CA
Birman; Mark - Santa Clara CA
Birman; Mark - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Organizing data in a hybrid memory for search operations Grant 9,269,411 - Estan , et al. February 23, 2	2016-02-23
Targeted search system with de-obfuscating functionality Grant 8,812,480 - Watson , et al. August 19, 2	2014-08-19
Content addressable memory having selectively interconnected shift register circuits Grant 8,631,195 - Khanna , et al. January 14, 2	2014-01-14
Organizing Data in a Hybrid Memory for Search Operations App 20130246697 - ESTAN; Cristian ; et al.	2013-09-19
Hybrid Memory for Search Operations App 20130246698 - ESTAN; Cristian ; et al.	2013-09-19
Pattern matching system and method for data streams, including deep packet inspection Grant 8,214,305 - Birman , et al. July 3, 2	2012-07-03
Compiling regular expressions for programmable content addressable memory devices Grant 7,924,590 - Starovoitov , et al. April 12, 2	2011-04-12
Reformulating regular expressions into architecture-dependent bit groups Grant 7,916,510 - Starovoitov , et al. March 29, 2	2011-03-29
Power reduction in a content addressable memory having programmable interconnect structure Grant 7,881,125 - Srinivasan , et al. February 1, 2	2011-02-01
Content addressable memory having selectively interconnected rows of counter circuits Grant 7,876,590 - Joshi , et al. January 25, 2	2011-01-25
Content Addressable Memory Having Selectively Interconnected Counter Circuits App 20100321971 - Joshi; Sachin ; et al.	2010-12-23
Content Addressable Memory Having Programmable Interconnect Structure App 20100321970 - Srinivasan; Maheshwaran ; et al.	2010-12-23
Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device Grant 7,836,246 - Birman , et al. November 16, 2	2010-11-16
Content addresable memory having selectively interconnected counter circuits Grant 7,826,242 - Joshi , et al. November 2, 2	2010-11-02
Content addresable memory having programmable interconnect structure Grant 7,821,844 - Srinivasan , et al. October 26, 2	2010-10-26
Content addressable memory having programmable combinational logic circuits Grant 7,787,275 - Birman , et al. August 31, 2	2010-08-31
Content Addresable Memory Having Selectively Interconnected Counter Circuits App 20100054013 - Joshi; Sachin ; et al.	2010-03-04
Content Addresable Memory Having Programmable Interconnect Structure App 20100054012 - Srinivasan; Maheshwaran ; et al.	2010-03-04
Content addresable memory having selectively interconnected counter circuits Grant 7,660,140 - Joshi , et al. February 9, 2	2010-02-09
Content addressable memory having programmable interconnect structure Grant 7,643,353 - Srinivasan , et al. January 5, 2	2010-01-05
Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device Grant 7,461,200 - Birman , et al. December 2, 2	2008-12-02
Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device App 20080263270 - Birman; Mark ; et al.	2008-10-23
Variable latency method and apparatus for floating-point coprocessor Grant 5,021,985 - Hu , et al. June 4, 1	1991-06-04
Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio Grant 4,901,267 - Birman , et al. February 13, 1	1990-02-13

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